公开(公告)号：US20020142519A1

公开(公告)日：2002-10-03

申请号：US10081296

申请日：2002-02-20

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Francois Leverd ,  Paul Ferreira

IPC: H01L021/44

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76841

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Abstract translation: 本发明涉及一种用于保护集成电路中的晶体管栅格的方法，用于制造跨越栅极的局部互连焊盘和形成在其上的硅衬底。 该方法包括在晶体管栅格上施加双电介质传导层，其中添加多晶硅层以便使用选择性原理，考虑到多晶硅相对于本地互连衬垫是 形成。 此外，根据本发明的方法，可以预先在晶体管和栅极的有源区上施加硅化处理。

公开(公告)号：US20030098493A1

公开(公告)日：2003-05-29

申请号：US10272444

申请日：2002-10-16

Applicant: STMicroelectronics S.A.

Inventor： Michel Marty ,  Francois Leverd ,  Philippe Coronel ,  Joaquin Torres

IPC: H01L021/8238 ,  H01L029/00

CPC classification number: H01L21/76229 ,  H01L21/764

Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

Abstract translation: 在半导体衬底中形成的隔离沟具有侧壁和底壁。 隔板在侧壁上并且彼此面对以在它们之间形成狭窄的通道。 底壁和间隔物涂覆有用于限定通道中的封闭空腔的电绝缘材料。 隔离沟槽适用于集成电路的制造。

公开(公告)号：US20020110976A1

公开(公告)日：2002-08-15

申请号：US10042520

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Philippe Coronel ,  Marc Piazza ,  Francois Leverd

IPC: H01L021/8242 ,  H01L021/4763 ,  H01L021/20

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

Abstract translation: 本发明涉及一种DRAM积分方法，其消除了用于插入位线接触的电容的上电极的光刻步骤固有的对准边缘。 上电极的去除在电容的下电极上自对准。 这是通过在要形成上电极的开口的位置处形成不同的形貌并在上电极上沉积非掺杂多晶硅层来实现的。 在该层上进行掺杂剂的注入，并且选择性地蚀刻位于显示区域差异的区域下部的非掺杂层的部分。 多晶硅层的剩余部分和位于下层的上部电极的一部分也被蚀刻。

公开(公告)号：US20020014676A1

公开(公告)日：2002-02-07

申请号：US09898540

申请日：2001-07-03

Applicant: STMicroelectronics S.A.

Inventor： Michel Marty ,  Helene Baudry ,  Francois Leverd

IPC: H01L029/00

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/763

Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.

Abstract translation: 在制造晶体管之前，在衬底中形成深绝缘沟槽的相位之后是在衬底中形成浅绝缘沟槽并延伸深沟槽的相位。 形成深沟槽的相位包括用初始氧化层涂覆深沟槽的内壁，并且在由绝缘材料形成的封套内的硅填充深沟槽。 形成浅沟槽的相位包括用初始氧化层涂覆浅沟槽的内壁，并用绝缘材料填充浅沟槽。

公开(公告)号：US20040033676A1

公开(公告)日：2004-02-19

申请号：US10421368

申请日：2003-04-23

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Francois Leverd ,  Thomas Skotnicki

IPC: H01L021/20 ,  H01L021/36

CPC classification number: H01L21/6835 ,  H01L21/32134 ,  H01L21/76251 ,  H01L23/544 ,  H01L27/10852 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648 ,  H01L51/0013 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/83894 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.

Abstract translation: 提供了一种用于制造集成电子部件的方法。 根据该方法，在第一基板的表面上产生初始结构。 该初始结构包含由差异化材料体积形成的限定图案。 包括限定图案的初始衬底的至少一部分被转移到第二衬底上，优选地通过使第一衬底相对于第二衬底反转，然后去除第一衬底。 然后在第二基板上产生另外的结构。 该附加结构包括与限定图案的一些体积不同的材料相对应放置的材料体积。 如此生产的电子部件可以根据技术或几何约束具有合适的构造。 在优选的方法中，对初始结构的转移部分应用选择性处理，以区分图案的差异材料的体积。