公开(公告)号：US20030098493A1

公开(公告)日：2003-05-29

申请号：US10272444

申请日：2002-10-16

Applicant: STMicroelectronics S.A.

Inventor： Michel Marty ,  Francois Leverd ,  Philippe Coronel ,  Joaquin Torres

IPC: H01L021/8238 ,  H01L029/00

CPC classification number: H01L21/76229 ,  H01L21/764

Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

Abstract translation: 在半导体衬底中形成的隔离沟具有侧壁和底壁。 隔板在侧壁上并且彼此面对以在它们之间形成狭窄的通道。 底壁和间隔物涂覆有用于限定通道中的封闭空腔的电绝缘材料。 隔离沟槽适用于集成电路的制造。

公开(公告)号：US20040262690A1

公开(公告)日：2004-12-30

申请号：US10817147

申请日：2004-04-02

Applicant: STMicroelectronics S.A.

Inventor： Philippe Coronel ,  Yves Morand ,  Thomas Skotnicki ,  Robin Cerutti

IPC: H01L027/148 ,  H01L029/768 ,  H01L029/76 ,  H01L021/336

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78645 ,  H01L29/78648

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract translation: 一种形成在硅衬底中的MOS晶体管，包括被绝缘壁包围的有源区域，覆盖有源区域的中心条带的第一导电条，放置在位于第一条带正上方的有源区域中的一个或多个第二导电条，以及导电 放置在绝缘壁的两个凹部中并且抵靠第一和第二条带的端部放置的区域，与导电条带和区域相对的硅表面被形成栅极氧化物的绝缘体覆盖。

公开(公告)号：US20020142519A1

公开(公告)日：2002-10-03

申请号：US10081296

申请日：2002-02-20

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Francois Leverd ,  Paul Ferreira

IPC: H01L021/44

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76841

Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

Abstract translation: 本发明涉及一种用于保护集成电路中的晶体管栅格的方法，用于制造跨越栅极的局部互连焊盘和形成在其上的硅衬底。 该方法包括在晶体管栅格上施加双电介质传导层，其中添加多晶硅层以便使用选择性原理，考虑到多晶硅相对于本地互连衬垫是 形成。 此外，根据本发明的方法，可以预先在晶体管和栅极的有源区上施加硅化处理。

公开(公告)号：US20040016968A1

公开(公告)日：2004-01-29

申请号：US10409653

申请日：2003-04-08

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L021/84 ,  H01L031/0392

CPC classification number: H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract translation: 提供一种半导体器件，其包括在半导体源极区域和半导体漏极区域之间沿纵向方向在半导体衬底上方延伸的半导体沟道区域和在横向方向上延伸的栅极区域，涂覆沟道区域并与 渠道区域。 源极，沟道和漏极区域形成在大致平面并平行于衬底的上表面的连续半导体层中。 此外，源极，漏极和栅极区域被涂覆在绝缘涂层中，以便在栅极区域和源极和漏极区域之间以及衬底与源极，漏极，栅极和沟道区域之间提供电绝缘。 还提供了一种包括这种半导体器件的集成电路及其制造方法。

公开(公告)号：US20030119219A1

公开(公告)日：2003-06-26

申请号：US10308482

申请日：2002-12-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Alexis Farcy ,  Philippe Coronel ,  Pascal Ancey ,  Joaquin Torres

IPC: H01L021/00 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: B81C1/0023 ,  B29C2043/5825

Abstract: The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

Abstract translation: 集成电路的制造包括制造电子芯片的第一阶段和产生放置在芯片上方的至少一个辅助部件并产生覆盖辅助部件的保护盖的第二阶段。 制造芯片的第一阶段从第一半导体衬底实现，并且包括形成位于芯片的选定区域中并且出现在芯片的上表面处的空腔。 第二生产阶段包括从第二半导体衬底生产辅助部件，与第一半导体衬底分离，然后放置在由第二衬底支撑的辅助部件的空腔中，以及将第二衬底与上表面的相互粘合 的芯片位于腔外。 第二基板然后也形成保护盖。

公开(公告)号：US20030016571A1

公开(公告)日：2003-01-23

申请号：US10176386

申请日：2002-06-20

Applicant: STMICROELECTRONICS S.A.

Inventor： Paul Ferreira ,  Philippe Coronel

IPC: G11C007/00

CPC classification number: H01L21/823892 ,  H01L21/033 ,  H01L21/266 ,  H01L21/823807

Abstract: The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of regions of the surface portion, the two groups of regions being mutually complementary with respect to the surface portion, the process making it possible to use only a single operation of positioning a mask which differentiates the regions of the first and second groups of regions, using the same protective materials for the regions of each group of regions against the effects of the treatment intended for the regions of the other group of regions. Application to the fabrication of semiconductor products.

Abstract translation: 本发明涉及一种根据彼此不同的第一和第二表面处理来处理基材表面的一部分的方法，分别用于第一组区域和第二组表面区域 部分，两组区域相对于表面部分互相互补，该方法使得仅使用仅使用相同保护材料来区分第一和第二组区域的掩模的单一定位操作 对于每个地区的区域，针对其他地区区域的治疗效果。 适用于制造半导体产品。

公开(公告)号：US20020110976A1

公开(公告)日：2002-08-15

申请号：US10042520

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Philippe Coronel ,  Marc Piazza ,  Francois Leverd

IPC: H01L021/8242 ,  H01L021/4763 ,  H01L021/20

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

Abstract translation: 本发明涉及一种DRAM积分方法，其消除了用于插入位线接触的电容的上电极的光刻步骤固有的对准边缘。 上电极的去除在电容的下电极上自对准。 这是通过在要形成上电极的开口的位置处形成不同的形貌并在上电极上沉积非掺杂多晶硅层来实现的。 在该层上进行掺杂剂的注入，并且选择性地蚀刻位于显示区域差异的区域下部的非掺杂层的部分。 多晶硅层的剩余部分和位于下层的上部电极的一部分也被蚀刻。

公开(公告)号：US20040033676A1

公开(公告)日：2004-02-19

申请号：US10421368

申请日：2003-04-23

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Francois Leverd ,  Thomas Skotnicki

IPC: H01L021/20 ,  H01L021/36

CPC classification number: H01L21/6835 ,  H01L21/32134 ,  H01L21/76251 ,  H01L23/544 ,  H01L27/10852 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648 ,  H01L51/0013 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/83894 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.

Abstract translation: 提供了一种用于制造集成电子部件的方法。 根据该方法，在第一基板的表面上产生初始结构。 该初始结构包含由差异化材料体积形成的限定图案。 包括限定图案的初始衬底的至少一部分被转移到第二衬底上，优选地通过使第一衬底相对于第二衬底反转，然后去除第一衬底。 然后在第二基板上产生另外的结构。 该附加结构包括与限定图案的一些体积不同的材料相对应放置的材料体积。 如此生产的电子部件可以根据技术或几何约束具有合适的构造。 在优选的方法中，对初始结构的转移部分应用选择性处理，以区分图案的差异材料的体积。