公开(公告)号：US20030034821A1

公开(公告)日：2003-02-20

申请号：US09955926

申请日：2001-09-18

Applicant: STMicroelectronics S.A.

Inventor： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

IPC: G06F001/04

CPC classification number: H01L27/10852 ,  H01L27/10882 ,  H01L27/10888

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

Abstract translation: 提供了一种集成电路，其具有包括局部掺杂的单晶衬底中形成的结的活性组分和位于活性组分之上的至少一个无源组分。 集成电路包括分离有源部件的第一绝缘层和无源部件的放宽，以及用于将无源部件与至少一个有源部件电连接的金属端子。 金属端子形成为第一绝缘层的厚度，并且具有从一个有源部件的接合极限突出的接触表面。 在优选实施例中，无源部件是电容器。 还提供了一种制造集成电路的方法，该集成电路包括MOS晶体管和矩阵中的DRAM单元的板载存储器平面。

公开(公告)号：US20020090781A1

公开(公告)日：2002-07-11

申请号：US10042506

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Catherine Mallardeau

IPC: H01L021/8242

CPC classification number: H01L27/1087 ,  H01L27/10832

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of Nnull doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

Abstract translation: 通过从硅衬底外延生长制造DRAM型电池的工艺包括生长硅锗层和硅层; 叠加第一层N +掺杂硅和第二层P掺杂硅; 以及在硅衬底上形成晶体管。 该方法还包括蚀刻晶体管的延伸中的沟槽，以提供在预定深度上相对于硅层访问硅锗层以形成横向空腔，以及在沟槽和侧向空腔中形成电容器 。