公开(公告)号：US20020076899A1

公开(公告)日：2002-06-20

申请号：US09920315

申请日：2001-08-01

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Michel Haond ,  Didier Dutartre

IPC: H01L021/76

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract translation: 提供了用于制造具有绝缘体上硅（SOI）或无硅（SON）结构的衬底的工艺，其可应用于半导体器件的制造，特别是诸如MOS，CMOS，BICMOS的晶体管 和HCMOS类型。 在制造工艺中，通过非选择性全晶片外延在衬底上生长多层叠层。 多层堆叠包括Ge或SiGe层上的硅层。 有源区被限定和掩蔽，并且绝缘垫被形成为以预定的间隔围绕每个有源区的周边定位并且抵靠有源区的侧壁放置。 绝缘沟槽被蚀刻，SiGe或Ge层被横向蚀刻，以便在硅层下方形成一个空洞。 沟槽填充有电介质。 在SOI结构的情况下，隧道填充有电介质。

公开(公告)号：US20020097608A1

公开(公告)日：2002-07-25

申请号：US10022185

申请日：2001-12-12

Applicant: STMICROELECTRONICS S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Michel Haond

IPC: G11C011/34

CPC classification number: H01L29/1054 ,  H01L29/0653 ,  H01L29/803

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

Abstract translation: 诸如光电子器件和集成半导体存储器件的电子器件包括至少一个集成的存储器点结构，其包括埋在该结构的衬底中并设置在晶体管的绝缘栅极之下的量子阱半导体区域。 偏置电压源适于偏置该结构以使能量子阱或量子阱外的电荷的充电或放电。

公开(公告)号：US20010053569A1

公开(公告)日：2001-12-20

申请号：US09812717

申请日：2001-03-20

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Malgorzata Jurczak ,  Michel Haond

IPC: H01L021/335

CPC classification number: H01L29/66772 ,  H01L29/78648

Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

Abstract translation: 制造MOS晶体管的方法包括在绝缘体上硅衬底内形成第一栅极，形成横向覆盖第一栅极的半导体沟道区，以及在沟道区的每一侧上形成半导体漏极和源极区。 半导体沟道区域和漏极和源极区域可以通过在第一栅极的上表面上外延生长。 通道区域可以通过在通道区域下形成隧道并且用第一电介质至少部分地填充隧道而与第一栅极的上表面隔离。 第二栅极形成在沟道区域上并且横向于沟道区域。 第二栅极可以通过第二电介质与沟道区的上表面分离。