公开(公告)号：US20020090781A1

公开(公告)日：2002-07-11

申请号：US10042506

申请日：2002-01-08

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Catherine Mallardeau

IPC: H01L021/8242

CPC classification number: H01L27/1087 ,  H01L27/10832

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of Nnull doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

Abstract translation: 通过从硅衬底外延生长制造DRAM型电池的工艺包括生长硅锗层和硅层; 叠加第一层N +掺杂硅和第二层P掺杂硅; 以及在硅衬底上形成晶体管。 该方法还包括蚀刻晶体管的延伸中的沟槽，以提供在预定深度上相对于硅层访问硅锗层以形成横向空腔，以及在沟槽和侧向空腔中形成电容器 。

公开(公告)号：US20020097608A1

公开(公告)日：2002-07-25

申请号：US10022185

申请日：2001-12-12

Applicant: STMICROELECTRONICS S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Michel Haond

IPC: G11C011/34

CPC classification number: H01L29/1054 ,  H01L29/0653 ,  H01L29/803

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

Abstract translation: 诸如光电子器件和集成半导体存储器件的电子器件包括至少一个集成的存储器点结构，其包括埋在该结构的衬底中并设置在晶体管的绝缘栅极之下的量子阱半导体区域。 偏置电压源适于偏置该结构以使能量子阱或量子阱外的电荷的充电或放电。

公开(公告)号：US20040016968A1

公开(公告)日：2004-01-29

申请号：US10409653

申请日：2003-04-08

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Coronel ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L021/84 ,  H01L031/0392

CPC classification number: H01L29/66772 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract translation: 提供一种半导体器件，其包括在半导体源极区域和半导体漏极区域之间沿纵向方向在半导体衬底上方延伸的半导体沟道区域和在横向方向上延伸的栅极区域，涂覆沟道区域并与 渠道区域。 源极，沟道和漏极区域形成在大致平面并平行于衬底的上表面的连续半导体层中。 此外，源极，漏极和栅极区域被涂覆在绝缘涂层中，以便在栅极区域和源极和漏极区域之间以及衬底与源极，漏极，栅极和沟道区域之间提供电绝缘。 还提供了一种包括这种半导体器件的集成电路及其制造方法。

公开(公告)号：US20020135020A1

公开(公告)日：2002-09-26

申请号：US10084255

申请日：2002-02-27

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Alexandre Villaret

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76289 ,  H01L29/66772

Abstract: The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract translation: 源极，漏极和沟道区域通过绝缘层在垂直于载体衬底完全隔离的硅层中产生，并且通过浅沟槽类型的横向隔离区域横向限定。