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    Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor
    1.
    发明申请
    Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor 有权
    用于制造具有异质结基极和相应晶体管的自对准双多晶硅型双极晶体管的方法

    公开(公告)号：US20010053584A1

    公开(公告)日：2001-12-20

    申请号：US09817898

    申请日：2001-03-26

    Applicant: STMicroelectronics S.A.

    Inventor： Alain Chantre ,  Didier Dutartre ,  Helene Baudry

    IPC: H01L021/76

    CPC classification number: H01L29/66242 ,  H01L29/7378

    Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

    Abstract translation: 具有异质结基底的自对准双多晶硅型双极晶体管包括位于半导体衬底的有源区上方的半导体异质结区域和界定有源区域的隔离区域，以及掺入晶体管的本征基极区域。 位于有源区上方并与半导体异质结区的上表面接触的发射极区。 形成晶体管的非本征基极区域的多晶硅层，位于发射极区域的每一侧，并且通过分离层与半导体异质结区域分离，所述分离层包括位于发射极区域正前方的导电连接部分。 该连接部件确保外部基座和内部基座之间的电接触。

    Process for fabricating a network of nanometric lines made of single-crystal silicon and device obtained
    2.
    发明申请
    Process for fabricating a network of nanometric lines made of single-crystal silicon and device obtained 有权
    制造由单晶硅制成的纳米线网络的方法和所获得的器件

    公开(公告)号：US20010005618A1

    公开(公告)日：2001-06-28

    申请号：US09738870

    申请日：2000-12-15

    Applicant: STMicroelectronics S.A.

    Inventor： Thomas Skotnicki ,  Malgorzata Jurczak ,  Didier Dutartre

    IPC: H01L021/00 ,  H01L021/84 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76262 ,  H01L29/0673 ,  H01L29/0676

    Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

    Abstract translation: 用于在隔离衬底上制造由单晶硅制成的纳米线网络的工艺包括制备包含限定主体中心部分的侧向隔离的硅体的衬底。 在具有由电介质材料制成的底壁的中心部分形成凹部，由电介质材料制成的第一对相对的平行侧壁和第二对相对的平行侧壁。 第二对的相对的平行侧壁中的至少一个由单晶硅形成。 该方法还包括从由凹槽的单晶硅制成的侧壁，由单晶SiGe合金和单晶硅制成的平行线的交替网络的凹槽中的外延生长。 此外，由单晶SiGe合金制成的线被蚀刻以在凹槽中形成由彼此绝缘的单晶硅硅制成的平行线的网络。

    Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
    4.
    发明申请
    Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic 失效
    在硅衬底上外延的方法，其包括重掺杂砷的区域

    公开(公告)号：US20020081374A1

    公开(公告)日：2002-06-27

    申请号：US09902497

    申请日：2002-01-15

    Applicant: STMicroelectronics S.A.

    Inventor： Didier Dutartre ,  Patrick Jerier

    IPC: B05D005/12

    CPC classification number: C30B29/06 ,  C23C16/24 ,  C30B25/20

    Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

    Abstract translation: 本发明涉及一种在硅基板上气相外延沉积硅的方法，该方法包括含有高浓度掺杂剂的区域，其中砷是砷，同时避免了砷的外延层的自掺杂，包括以下步骤：执行第一薄外延 沉积，然后退火; 第一外延沉积和退火的条件和持续时间使得砷扩散长度远低于在第一沉积中形成的层的厚度; 以及对所选择的持续时间进行第二外延沉积以获得期望的总厚度。

    Process for fabricating a substrate of the silicon-on-insulator or silicon-on-nothing type and resulting device
    5.
    发明申请
    Process for fabricating a substrate of the silicon-on-insulator or silicon-on-nothing type and resulting device 有权
    用于制造绝缘体上硅或无硅无机型及其所得器件的衬底的工艺

    公开(公告)号：US20020076899A1

    公开(公告)日：2002-06-20

    申请号：US09920315

    申请日：2001-08-01

    Applicant: STMicroelectronics S.A.

    Inventor： Thomas Skotnicki ,  Michel Haond ,  Didier Dutartre

    IPC: H01L021/76

    CPC classification number: H01L21/76264 ,  H01L21/76283

    Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

    Abstract translation: 提供了用于制造具有绝缘体上硅（SOI）或无硅（SON）结构的衬底的工艺，其可应用于半导体器件的制造，特别是诸如MOS，CMOS，BICMOS的晶体管 和HCMOS类型。 在制造工艺中，通过非选择性全晶片外延在衬底上生长多层叠层。 多层堆叠包括Ge或SiGe层上的硅层。 有源区被限定和掩蔽，并且绝缘垫被形成为以预定的间隔围绕每个有源区的周边定位并且抵靠有源区的侧壁放置。 绝缘沟槽被蚀刻，SiGe或Ge层被横向蚀刻，以便在硅层下方形成一个空洞。 沟槽填充有电介质。 在SOI结构的情况下，隧道填充有电介质。

    Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor
    6.
    发明申请
    Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor 有权
    制造双晶硅，异质结基极型和相应晶体管的双极晶体管的方法

    公开(公告)号：US20020185657A1

    公开(公告)日：2002-12-12

    申请号：US10097651

    申请日：2002-03-13

    Applicant: STMICROELECTRONICS S.A.

    Inventor： Alain Chantre ,  Helene Baudry ,  Didier Dutartre

    IPC: H01L031/0328

    CPC classification number: H01L29/66242 ,  H01L29/7378

    Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

    Abstract translation: 晶体管和双晶硅异质结基极型双极晶体管的制造方法，其中具有SiGe异质结的半导体层通过非选择性外延在衬底的有源区和围绕有源区的绝缘区形成。 在有源区域的一部分上方的半导体层上形成至少一个阻挡层。 在半导体层和停止层的一部分上形成多晶硅层和上绝缘层，留下发射器窗口。 发射极区域通过在发射极窗中外延形成，部分地搁置在上绝缘层上并与半导体层接触。

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