公开(公告)号：US20020186592A1

公开(公告)日：2002-12-12

申请号：US10118660

申请日：2002-04-08

Applicant: STMicroelectronics S.r.I.

Inventor： Mauro Pagliato ,  Paolo Rolandi ,  Massimo Montanaro

IPC: G11C011/34

CPC classification number: G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5632

Abstract: Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.

Abstract translation: 这里描述的是一种异步串行二点读出放大器，它包括第一比较器级，该第一比较器级具有接收在多级存储器单元中流动的单元电流的第一输入，其内容将被读取，接收第一参考电流的第二输入和输出 提供存储在多层存储单元中的第一位; 多路复用器级，其具有连接到第一比较器级的输出的选择输入，接收第二参考电流的第一信号输入，接收第三参考电流的第二信号输入和可选地可连接到第一或第二信号的信号 输入取决于选择输入上存在的逻辑电平; 以及第二比较器级，其具有接收单元电流的第一输入，连接到多路复用器级的信号输出的第二输入和提供存储在多电平存储单元中的第二位的输出。

公开(公告)号：US20030076718A1

公开(公告)日：2003-04-24

申请号：US10259252

申请日：2002-09-26

Applicant: STMicroelectronics S.r.I

Inventor： Paolo Rolandi

IPC: G11C007/00

CPC classification number: G11C19/282 ,  G11C11/5628 ,  G11C11/5642

Abstract: According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; ifit is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

Abstract translation: 根据多级编程方法，每个存储器位置可以以非二进制数的级编程。 要存储在两个位置中的位被分成两组，其中第一组定义高于非二进制数量级的级数。 在编程期间，如果要写入的第一组位对应于小于非二进制数量级的数字，则将第一组位写入第一位置，并将第二组位写入第二位置; 如果大于非二进制数量级，则将第一组位写入第二位置，并将第二组位写入第一位置。 第二位置中的第一组的位相对于第二组的位被存储在不同的电平。

公开(公告)号：US20020021582A1

公开(公告)日：2002-02-21

申请号：US09898744

申请日：2001-07-03

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: G11C011/34

CPC classification number: G11C16/08 ,  G11C16/0491 ,  H01L27/115

Abstract: A non-volatile memory matrix architecture, having a virtual ground monolithically integrated on a semiconductor substrate, includes a plurality of memory cells organized into matrix blocks. The matrix blocks are placed on rows and columns and are associated with respective row and column decoding circuits. The memory blocks are separated from each other by at least one insulation stripe which is parallel to the columns. The non-volatile memory matrix architecture further includes a pass-transistor decoding circuit with a number of levels corresponding to the number of rows to select.

Abstract translation: 具有单片集成在半导体衬底上的虚拟接地的非易失性存储矩阵体系包括被组织成矩阵块的多个存储单元。 矩阵块被放置在行和列上并且与相应的行和列解码电路相关联。 存储块通过平行于列的至少一个绝缘条彼此分离。 非易失性存储器矩阵架构还包括具有对应于要选择的行数的多个级别的传输晶体管解码电路。

公开(公告)号：US20040130948A1

公开(公告)日：2004-07-08

申请号：US10742181

申请日：2003-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: G11C016/04 ,  G11C011/34

CPC classification number: G11C16/08 ,  G11C8/10

Abstract: A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

公开(公告)号：US20040008090A1

公开(公告)日：2004-01-15

申请号：US10406628

申请日：2003-04-03

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: H03B001/00

CPC classification number: H03K3/0315 ,  H03L7/00

Abstract: An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.

Abstract translation: 可变频振荡电路包括：奇数个反相器连接成一个环路; 多个电容元件，各自连接到各个逆变器的输出端子; 以及输出端子，其提供以振荡频率振荡的信号。 振荡器电路还包括校准电路，用于校准可由反相器传送到各个电容元件的最大电流。

公开(公告)号：US20020021596A1

公开(公告)日：2002-02-21

申请号：US09881581

申请日：2001-06-14

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: G11C029/00

CPC classification number: G11C16/102 ,  G11C7/16 ,  G11C16/18

Abstract: An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and an electrically programmable non-volatile memory for storing the data in digital format. The memory includes a first terminal for receiving a programming signal for enabling storage of the data, and a second terminal for receiving a reading signal for enabling output of the stored data via the input/output terminals. A memory control circuit is connected to the first and second terminals of the electrically programmable non-volatile memory, and to the input/output terminals for generating programming and reading signals based upon the command signal. The electrically programmable non-volatile memory is erasable by electromagnetic radiation for permitting a non-electrical erasure of the stored data.

Abstract translation: 一种用于存储数据并用于应用于与外部采集系统和外部处理系统中的至少一个协同操作的存储卡的集成电路，包括用于接收要存储的数据的输入/输出端子， 用于以数字格式存储数据的非易失性存储器。 存储器包括用于接收用于使数据存储的编程信号的第一端子，以及用于接收经由输入/输出端子输出存储的数据的读取信号的第二端子。 存储器控制电路连接到电可编程非易失性存储器的第一和第二端子以及输入/输出端子，用于基于该命令信号产生编程和读取信号。 电可编程非易失性存储器可通过电磁辐射进行擦除，以允许存储数据的非电擦除。