公开(公告)号：US20240212751A1

公开(公告)日：2024-06-27

申请号：US18543847

申请日：2023-12-18

Applicant: STMicroelectronics S.r.l.

Inventor： Riccardo ZURLA ,  Marco PASOTTI ,  Marcella CARISSIMI ,  Alessandro CABRINI

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/004 ,  G06F17/16 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C2213/79

Abstract: A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.