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公开(公告)号：US20230311801A1
公开(公告)日：2023-10-05
申请号：US17711681
申请日：2022-04-01
Applicant: STMicroelectronics S.r.l.
Inventor： Gerardo Castellano , Antonio Giordano , Marcello Raimondi
IPC: B60R21/015
CPC classification number: B60R21/01512 , B60R2021/01211
Abstract: A method to arm an airbag, the method including determining, by a system device, that an arming condition for the airbag has been met; delivering a communication to a master device from the system device to inform the master device that the arming condition has been met; snooping the communication by an expansion device; and arming the airbag by the expansion device in response to snooping the arming condition.
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Patent Agency Ranking
公开(公告)号：US11557891B2
公开(公告)日：2023-01-17
申请号：US17454228
申请日：2021-11-09
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Antonio Giordano , Orazio Pennisi , Leonardo Pedone , Luca Finazzi
Abstract: A circuit includes comparator circuitry to sense a current through a load and compare the intensity of the current with a comparison threshold which can be set to a first, lower threshold value and a second, higher threshold value. Logic circuitry receives from the comparator circuitry a comparison signal having a first value or a second value based on whether the intensity is lower or higher than the comparison threshold. The logic circuitry is configured to assert a first overcurrent event signal or a second overcurrent event signal based on the comparison signal having the first value or the second value and the comparison threshold set to the first or second threshold value.
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公开(公告)号：US11817864B2
公开(公告)日：2023-11-14
申请号：US17839813
申请日：2022-06-14
Applicant: STMicroelectronics S.r.l.
Inventor： Luigi Sole , Antonio Giordano
Abstract: In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the reference signal, a slave timing stage and a slave synchronization stage.
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公开(公告)号：US20220416794A1
公开(公告)日：2022-12-29
申请号：US17839813
申请日：2022-06-14
Applicant: STMicroelectronics S.r.l.
Inventor： Luigi Sole , Antonio Giordano
Abstract: In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the reference signal, a slave timing stage and a slave synchronization stage.
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公开(公告)号：US12038799B2
公开(公告)日：2024-07-16
申请号：US17903753
申请日：2022-09-06
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Luigi Sole , Rossella Gaudiano , Marta Cantarini , Nicola Errico , Antonio Giordano
IPC: G06F1/32 , G06F1/3206 , G06F1/3296
CPC classification number: G06F1/3206 , G06F1/3296
Abstract: A system basis chip is described. The system basis chip comprises a power supply circuit configured to receive an input voltage and generate a plurality of voltages, and a control circuit. Specifically, the power supply circuit is configured to selectively switch on a first and a second voltage of the voltages as a function of a control signal. The control circuit measures a resistance value of an external resistor connected to a terminal and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration indicates that said first voltage should be switched on before said second voltage and a second configuration indicates that said second voltage should be switched on before said first voltage. Accordingly, the control circuit may generate the control signal in order to switch on in sequence the first and the second voltage according to the selected configuration.
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公开(公告)号：US20220190585A1
公开(公告)日：2022-06-16
申请号：US17454228
申请日：2021-11-09
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Antonio Giordano , Orazio Pennisi , Leonardo Pedone , Luca Finazzi
Abstract: A circuit includes comparator circuitry to sense a current through a load and compare the intensity of the current with a comparison threshold which can be set to a first, lower threshold value and a second, higher threshold value. Logic circuitry receives from the comparator circuitry a comparison signal having a first value or a second value based on whether the intensity is lower or higher than the comparison threshold. The logic circuitry is configured to assert a first overcurrent event signal or a second overcurrent event signal based on the comparison signal having the first value or the second value and the comparison threshold set to the first or second threshold value.
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