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公开(公告)号:US12015515B2
公开(公告)日:2024-06-18
申请号:US17845860
申请日:2022-06-21
发明人: Valerio Bendotti , Nicola De Campo , Carlo Curina
IPC分类号: H04L27/36 , H03K17/687 , H03K19/096 , H03K19/21 , H04L25/40
CPC分类号: H04L27/36 , H03K17/687 , H03K19/096 , H03K19/21 , H04L25/40
摘要: A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.