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公开(公告)号：US11312238B2
公开(公告)日：2022-04-26
申请号：US16893771
申请日：2020-06-05
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vittorio D'Angelo , Paolo Turbanti
Abstract: A method can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A faulty condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is swapped for a first swapped voltage drop between a common terminal and the second terminal of the second battery cell.
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公开(公告)号：US11079442B2
公开(公告)日：2021-08-03
申请号：US16420992
申请日：2019-05-23
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vanni Poletto , Vittorio D'Angelo
Abstract: A method of operating a control device includes performing an open load test or a current leakage test. The open load test includes activating a first current and then a second current and sensing with the first current and the second current activated, respectively, a first voltage drop and a second voltage drop between charge distribution pins and charge sensing pins of the control device. Respective differences are calculated between the first voltage drop and the second voltage drop sensed with the first current and the second current activated, respectively. These differences are compared with respective thresholds and an open circuit condition is declared as a result of the differences calculated reaching these thresholds.
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3.发明授权公开(公告)号：US12191850B2
公开(公告)日：2025-01-07
申请号：US18328266
申请日：2023-06-02
Applicant: STMicroelectronics S.r.l.
Inventor： Vittorio D′Angelo , Salvatore Cannavacciuolo , Valerio Bendotti , Paolo Selvo , Diego Alagna
IPC: H03K17/00 , H03K3/017 , H03K7/08 , H03K17/18 , H03K17/567 , H03K17/687 , H03K17/689 , H03M1/50
Abstract: In an embodiment a method includes receiving, at an input of a low-voltage section of a gate driver, a PWM control signal with a switching frequency, providing, at an output of a high-voltage section of the gat driver, a gate-driving signal as a function of the PWM control signal to a power stage, wherein the high-voltage section is galvanically isolated from the low-voltage section, receiving, at a feedback input of the high-voltage section, at least one feedback signal indicative of an operation of the power stage, converting, at an ADC module of the high-voltage section, the feedback signal into a digital data stream, providing, to the ADC module, a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal and sending, via an isolation communication channel between the low-voltage section and the high-voltage section, the digital data stream to the low-voltage section.
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4.发明授权公开(公告)号：US11722133B2
公开(公告)日：2023-08-08
申请号：US17807519
申请日：2022-06-17
Applicant: STMicroelectronics S.r.l.
Inventor： Vittorio D'Angelo , Salvatore Cannavacciuolo , Valerio Bendotti , Paolo Selvo , Diego Alagna
IPC: H03K17/00 , H03K17/567 , H03K3/017 , H03K7/08 , H03K17/687 , H03K17/689 , H03M1/50
CPC classification number: H03K17/567 , H03K3/017 , H03K7/08 , H03K17/687 , H03K17/689 , H03M1/504
Abstract: In an embodiment an isolated gate driver device includes a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage, a high-voltage section, galvanically isolated from the low-voltage section the high-voltage section including a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch, a feedback input configured to receive at least one feedback signal indicative of an operation of the power stag, and an ADC module configured to convert the feedback signal into a digital data stream and a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal.
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公开(公告)号：US11979143B2
公开(公告)日：2024-05-07
申请号：US17870173
申请日：2022-07-21
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Valerio Bendotti , Luca Finazzi , Gaudenzia Bagnati
CPC classification number: H03K17/162 , H02M3/158 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20230006667A1
公开(公告)日：2023-01-05
申请号：US17807519
申请日：2022-06-17
Applicant: STMicroelectronics S.r.l
Inventor： Vittorio D'Angelo , Salvatore Cannavacciuolo , Valerio Bendotti , Paolo Selvo , Diego Alagna
IPC: H03K17/567 , H03K17/689 , H03K7/08 , H03K3/017 , H03M1/50
Abstract: In an embodiment an isolated gate driver device includes a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage, a high-voltage section, galvanically isolated from the low-voltage section the high-voltage section including a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch, a feedback input configured to receive at least one feedback signal indicative of an operation of the power stag, and an ADC module configured to convert the feedback signal into a digital data stream and a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal.
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公开(公告)号：US11888304B2
公开(公告)日：2024-01-30
申请号：US16666989
申请日：2019-10-29
Applicant: STMicroelectronics S.r.l.
Inventor： Vittorio D'Angelo , Salvatore Cannavacciuolo , Sergio Lecce , Valerio Bendotti , Orazio Pennisi
CPC classification number: H02H1/063 , H02H9/046 , H02J7/0014
Abstract: An integrated circuit with a hot-plug protection circuit includes input pins and an output pin. The input pins are electrically coupled to a common node in the hot-plug protection circuit via respective electrical connections. The integrated circuit includes clamping circuitry coupled between the common node and the output pin, the clamping circuitry activatable as a result of a voltage spike applied across the clamping circuitry. The plurality of electrical connections and the clamping circuitry provide respective current discharge paths between the input pins in the input pins and the output pin, the respective current discharge paths configured to become conductive as a result of a voltage spike applied to any of the input pins in the plurality of input pins being transferred to the common node via the respective electrical connection in the plurality of electrical connections electrically coupling said any of said input pins to the common node.
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公开(公告)号：US20220219544A1
公开(公告)日：2022-07-14
申请号：US17711543
申请日：2022-04-01
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vittorio D'Angelo , Paolo Turbanti
Abstract: A method can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A faulty condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is swapped for a first swapped voltage drop between a common terminal and the second terminal of the second battery cell.
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公开(公告)号：US11077755B2
公开(公告)日：2021-08-03
申请号：US16420875
申请日：2019-05-23
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vanni Poletto
IPC: B60L3/00 , G01R31/385 , B60L50/64 , H02J7/00 , H03M3/00
Abstract: A circuit includes a differential stage configured to provide a differential output signal. An analog-to-digital converter is coupled to first and second output nodes of the differential stage. The analog-to-digital converter is configured to provide an output signal that is a function of the differential output signal from the differential stage. A multiplexer is configured to receive a differential input signal. The multiplexer includes a test switch switchable between a conductive state and a non-conductive state. In the conductive state, the test switch couples the first input node and the second input node of the differential stage. Test signal injection circuitry is activatable to force a differential current through the differential stage. The circuit is selectively switchable between an operational mode and a self-test mode.
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10.发明授权公开(公告)号：US12095603B2
公开(公告)日：2024-09-17
申请号：US18146872
申请日：2022-12-27
Applicant: STMicroelectronics S.r.l.
Inventor： Valerio Bendotti , Valerio Gennari Santori
CPC classification number: H04L27/20 , H03K19/20 , H04B1/0466 , H04B1/16 , H04L25/4902
Abstract: An isolated driver device comprises a first semiconductor die and a second semiconductor die galvanically isolated from each other. The second semiconductor die includes a signal modulator circuit configured to modulate a carrier signal to produce a modulated signal encoding information. A galvanically isolated communication channel implemented in the first semiconductor die and the second semiconductor die is configured to transmit the modulated signal from the second semiconductor die to the first semiconductor die. The second semiconductor die includes: a fault detection circuit configured to detect electrical faults in the second semiconductor die; a logic circuit coupled to the fault detection circuit and configured to assert a modulation bypass signal in response to a fault being detected by the fault detection circuit; and modulation masking circuitry configured to force the modulated signal to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal being asserted. The first semiconductor die includes a respective logic circuit sensitive to the modulated signal and configured to detect a condition where the modulated signal has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal in response to the condition being detected.
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