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公开(公告)号：US20180159538A1
公开(公告)日：2018-06-07
申请号：US15607588
申请日：2017-05-29
IPC分类号： H03K19/21
CPC分类号： H03K19/21 , G08C2201/91 , H03K19/1733 , H03K19/1737 , H03K2217/94021 , H04L61/2038 , H04L61/6072
摘要： A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
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公开(公告)号：US20190013813A1
公开(公告)日：2019-01-10
申请号：US16105424
申请日：2018-08-20
IPC分类号： H03K19/21 , H03K19/173 , H04L29/12
CPC分类号： H03K19/21 , G08C2201/91 , H03K19/1733 , H03K19/1737 , H03K2217/94021 , H04L61/2038 , H04L61/6072
摘要： A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
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公开(公告)号：US10135733B2
公开(公告)日：2018-11-20
申请号：US15334070
申请日：2016-10-25
IPC分类号： H04L12/741 , H04L1/00 , H04L29/06 , H04W52/02
摘要： A receiver circuit extracts data from a serial data signal. The serial data signal contains a data packet having a first format with a first number of bits or a second format with a second number of bits based on a selection signal. The second format comprises the bits of the first format followed by one or more additional bits. The receiver circuit has at least one shift register having a total number of bits equal or greater than the number of bits of the second format and a switching circuit that selectively connects the serial data signal to one of the shift register serial inputs as a function of the selection signal. When the first format is selected and the respective bits received, the bits are stored in given positions of the one or more shift registers. The switching circuit also, when the second format is selected and the respective bits received, stores the bits of the first format included at the beginning of the second format in the same given positions of the one or more shift registers.
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公开(公告)号：US10084455B2
公开(公告)日：2018-09-25
申请号：US15607588
申请日：2017-05-29
CPC分类号： H03K19/21 , G08C2201/91 , H03K19/1733 , H03K19/1737 , H03K2217/94021 , H04L61/2038 , H04L61/6072
摘要： A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
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公开(公告)号：US20180019946A1
公开(公告)日：2018-01-18
申请号：US15334070
申请日：2016-10-25
IPC分类号： H04L12/741 , H04L1/00 , H04L29/06 , H04W52/02
CPC分类号： H04L45/745 , H04L1/0053 , H04L1/0061 , H04L1/0078 , H04L69/22 , H04W52/0229 , Y02D70/00
摘要： A receiver circuit extracts data from a serial data signal. The serial data signal contains a data packet having a first format with a first number of bits or a second format with a second number of bits based on a selection signal. The second format comprises the bits of the first format followed by one or more additional bits. The receiver circuit has at least one shift register having a total number of bits equal or greater than the number of bits of the second format and a switching circuit that selectively connects the serial data signal to one of the shift register serial inputs as a function of the selection signal. When the first format is selected and the respective bits received, the bits are stored in given positions of the one or more shift registers. The switching circuit also, when the second format is selected and the respective bits received, stores the bits of the first format included at the beginning of the second format in the same given positions of the one or more shift registers.
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公开(公告)号：US10566978B2
公开(公告)日：2020-02-18
申请号：US16105424
申请日：2018-08-20
IPC分类号： H03K19/21 , H03K19/173 , H04L29/12
摘要： A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
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