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公开(公告)号：US11798603B2
公开(公告)日：2023-10-24
申请号：US18175375
申请日：2023-02-27
发明人： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC分类号： G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
CPC分类号： G11C7/12 , G11C7/065 , G11C7/222 , G11C11/4091 , G11C11/4094
摘要： A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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公开(公告)号：US11615823B2
公开(公告)日：2023-03-28
申请号：US17542203
申请日：2021-12-03
发明人： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC分类号： G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
摘要： A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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公开(公告)号：US20230110870A1
公开(公告)日：2023-04-13
申请号：US17490976
申请日：2021-09-30
发明人： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
摘要： A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US11615820B1
公开(公告)日：2023-03-28
申请号：US17490976
申请日：2021-09-30
发明人： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
摘要： A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US11205462B2
公开(公告)日：2021-12-21
申请号：US17010704
申请日：2020-09-02
发明人： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC分类号： G11C7/10 , G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
摘要： A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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6.发明授权公开(公告)号：US11935607B2
公开(公告)日：2024-03-19
申请号：US17837377
申请日：2022-06-10
发明人： Vikas Rana , Vivek Tyagi
CPC分类号： G11C29/12005 , G11C29/18 , G11C29/4401 , G11C29/52 , G11C2029/1202 , G11C2029/1204 , G11C2029/1802
摘要： An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.
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