公开(公告)号：US20130201771A1

公开(公告)日：2013-08-08

申请号：US13758536

申请日：2013-02-04

Applicant: STMicroelectronics SA

Inventor： Anis Feki ,  Jean-Christophe Lafont ,  David Turgis

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C8/00 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/419 ,  G11C13/0069 ,  G11C14/0054

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract translation: 包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。 存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。 存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。 第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。 第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。

公开(公告)号：US20140347906A1

公开(公告)日：2014-11-27

申请号：US14280833

申请日：2014-05-19

Applicant: STMicroelectronics SA

Inventor： Olivier Menut ,  David Turgis ,  Lorenzo Ciampolini

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G11C15/04

Abstract: A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data item) and a second storage cell (storing a potential representing the second reference binary data item). A comparison circuit is connected to the first and second storage circuits and to the input terminal SL. A comparison node presents a potential representing the comparison of the input binary data item with the first and second reference data items. The comparison node is connected to an output stage, and the output stage is connected to the match line. The signal on the match line is based on the potential of the comparison node.

Abstract translation: 三元内容寻址单元被配置为将输入端上存在的输入二进制数据项与两个参考二进制数据项进行比较，并在匹配线上输出匹配信号。 小区包括：第一存储电路（存储表示第一参考二进制数据项的电位）和第二存储单元（存储表示第二参考二进制数据项的电位）。 比较电路连接到第一和第二存储电路和输入端子SL。 比较节点呈现表示输入二进制数据项与第一和第二参考数据项的比较的潜力。 比较节点连接到输出级，输出级连接到匹配线。 匹配线上的信号基于比较节点的电位。

公开(公告)号：US08891317B2

公开(公告)日：2014-11-18

申请号：US13758536

申请日：2013-02-04

Applicant: STMicroelectronics SA

Inventor： Anis Feki ,  Jean-Christophe Lafont ,  David Turgis

IPC: G11C8/00 ,  G11C7/00 ,  G11C5/06 ,  G11C5/02 ,  G11C11/419 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C7/00 ,  G11C8/00 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/419 ,  G11C13/0069 ,  G11C14/0054

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract translation: 包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。 存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。 存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。 第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。 第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。