公开(公告)号：US20130201771A1

公开(公告)日：2013-08-08

申请号：US13758536

申请日：2013-02-04

Applicant: STMicroelectronics SA

Inventor： Anis Feki ,  Jean-Christophe Lafont ,  David Turgis

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C8/00 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/419 ,  G11C13/0069 ,  G11C14/0054

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract translation: 包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。 存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。 存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。 第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。 第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。

公开(公告)号：US08891317B2

公开(公告)日：2014-11-18

申请号：US13758536

申请日：2013-02-04

Applicant: STMicroelectronics SA

Inventor： Anis Feki ,  Jean-Christophe Lafont ,  David Turgis

IPC: G11C8/00 ,  G11C7/00 ,  G11C5/06 ,  G11C5/02 ,  G11C11/419 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C7/00 ,  G11C8/00 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/419 ,  G11C13/0069 ,  G11C14/0054

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract translation: 包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。 存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。 存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。 第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。 第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。