公开(公告)号：US06001461A

公开(公告)日：1999-12-14

申请号：US771388

申请日：1996-12-19

申请人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

发明人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

IPC分类号： H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  B32B9/00

CPC分类号： H01L23/532 ,  H01L21/32051 ,  H01L23/5283 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10T428/2457 ,  Y10T428/24926

摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.

摘要翻译： 一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。 一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界 相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。 一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个 选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

公开(公告)号：US5709958A

公开(公告)日：1998-01-20

申请号：US451528

申请日：1995-05-26

申请人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

发明人： Hiroshi Toyoda ,  Hisashi Kaneko ,  Masahiko Hasunuma ,  Takashi Kawanoue ,  Hiroshi Tomita ,  Akihiro Kajita ,  Masami Miyauchi ,  Takashi Kawakubo ,  Sachiyo Ito

IPC分类号： H01L21/3205 ,  H01L23/528 ,  H01L23/532 ,  H01L29/43

CPC分类号： H01L21/32051 ,  H01L23/5283 ,  H01L23/532 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10T428/12528 ,  Y10T428/12674 ,  Y10T428/12681

摘要： An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.

摘要翻译： 一种电子部件，包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。 一种电子部件，其具有由高取向晶体形成的金属布线，其中所有晶界的一半以上是由倾斜，旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界 相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。 一种电子部件的制造方法，其特征在于，包括以下步骤：通过绝缘层，阻挡层，接触层或无定形薄膜层，在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤，其中一个 选自Ga，In，Cd，Bi，Pb，Sn和Tl的元素在导体层的沉积之前或期间提供。

公开(公告)号：US06975033B2

公开(公告)日：2005-12-13

申请号：US10247378

申请日：2002-09-20

申请人： Sachiyo Ito ,  Masahiko Hasunuma ,  Takashi Kawanoue

发明人： Sachiyo Ito ,  Masahiko Hasunuma ,  Takashi Kawanoue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate on which an element is formed, a low dielectric constant insulation film formed over the semiconductor substrate and having a relative dielectric constant of 3 or lower, a plug and a wiring layer buried in the low dielectric constant insulation film, and a high Young's modulus insulation film having a Young's modulus of 15 GPa or higher and formed in contact with a side of the plug between the low dielectric constant insulation film and the plug.

摘要翻译： 半导体器件包括其上形成有元件的半导体衬底，形成在半导体衬底上并具有3或更低的相对介电常数的低介电常数绝缘膜，埋入低介电常数绝缘膜中的插塞和布线层 以及杨氏模量为15GPa以上的高杨氏模量绝缘膜，并且与低介电常数绝缘膜和插塞之间的插塞侧接触形成。

公开(公告)号：US20070204243A1

公开(公告)日：2007-08-30

申请号：US11703218

申请日：2007-02-07

申请人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

发明人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

IPC分类号： G06F17/50 ,  G06F17/10 ,  G06F19/00 ,  G01L19/00

CPC分类号： G06F17/5018 ,  G06F17/5068 ,  G06F2217/80 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

摘要翻译： 提供一种应力分析方法，包括：通过使用分割单元将芯片的内部划分为多个分析区域，通过使用复合特性导出单元导出多个分析区域的物理属性值的复合特性 基于多个分析区域中的每一个的布线结构数据，分析包括在分析区域中的材料，并且基于多个分析区域中的每一个，分别对每个分析区域进行复合，并且通过使用应力分析单元来创建三维模型 使用每个分析区域作为元素的有限元法，将复合属性应用于每个元素，并进行应力分析。

公开(公告)号：US06580171B2

公开(公告)日：2003-06-17

申请号：US10085067

申请日：2002-03-01

申请人： Sachiyo Ito ,  Masahiko Hasunuma

发明人： Sachiyo Ito ,  Masahiko Hasunuma

IPC分类号： H01L23522

CPC分类号： H01L23/5329 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor device is structured to include a wiring made of Al, a first insulation film made of silicon oxide including an organic content formed in contact with an upper surface of the wiring, and a second insulation film formed in contact with an upper surface of the first insulation film and made of an F-added SiO2 film having a higher Young's modulus than that of the first insulation film. The wiring has a film thickness dM of 400 nm, the first insulation film has a film thickness ds of 400 nm, and the second insulation film has a film thickness dh of 10 nm.

公开(公告)号：US06403462B1

公开(公告)日：2002-06-11

申请号：US09321848

申请日：1999-05-28

申请人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

发明人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

IPC分类号： H01L214763

CPC分类号： H01L21/76847 ,  H01L21/32051 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

摘要翻译： 本发明的半导体器件制造方法具有在半导体衬底上形成层间绝缘膜的步骤，在层间绝缘膜中形成互连槽的步骤，用导电膜填充互连槽的内部的步骤 由第一物质制成并且比互连槽的深度厚，在Al膜同时或在Al膜形成之后热稳定晶粒尺寸的步骤，形成 Al膜上的Cu膜，通过使Cu选择性地扩散到Al膜的晶粒边界并允许θ相层分割Al膜，在Al膜的晶粒边界中选择性地形成θ相层的步骤 在互连槽中成为比Blech临界长度短的精细Al互连，以及除去Interconnec外部的Al膜和Cu膜的步骤 沟槽。

公开(公告)号：US07921401B2

公开(公告)日：2011-04-05

申请号：US11703218

申请日：2007-02-07

申请人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

发明人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5018 ,  G06F17/5068 ,  G06F2217/80 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

摘要翻译： 提供一种应力分析方法，包括：通过使用分割单元将芯片的内部划分为多个分析区域，通过使用复合特性导出单元导出多个分析区域的物理属性值的复合特性 基于多个分析区域中的每一个的布线结构数据，分析包括在分析区域中的材料，并且基于多个分析区域中的每一个，分别对每个分析区域进行复合，并且通过使用应力分析单元来创建三维模型 使用每个分析区域作为元素的有限元法，将复合属性应用于每个元素，并进行应力分析。

公开(公告)号：US07872353B2

公开(公告)日：2011-01-18

申请号：US11964336

申请日：2007-12-26

申请人： Sachiyo Ito ,  Masahiko Hasunuma

发明人： Sachiyo Ito ,  Masahiko Hasunuma

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.4 or less respectively, a plurality of wirings provided at least one within each of the interlayer-insulator-film and at least partially located within the low-relative-dielectric-constant-films, a plurality of plugs provided at least one within each of the interlayer-insulator-film and connected to a lower part of the wirings, and a plurality of reinforcement members provided at least one within each of the interlayer-insulator-film with being separated from the wirings at a predetermined interval, electrically cut from the wirings and the plugs, and at least partially located within the low-relative-dielectric-constant-films, and wherein, the interlayer-insulator-films, the wirings, the plugs, and the reinforcement members satisfy a predetermined relation for each of the interlayer-insulator-film.

摘要翻译： 一种半导体器件，包括层叠在衬底上的至少两层层间绝缘膜，并且至少部分由相对介电常数为3.4以下的低相对介电常数膜形成，多个 布线在每个层间绝缘膜内提供至少一个，并且至少部分地位于低相对介电常数膜内;多个插塞，其设置在每个层间绝缘膜内至少一个并连接 连接到布线的下部，以及多个加强构件，其在每个层间绝缘体膜内设置有至少一个预定间隔的布线，从布线和插塞电切割，并且至少 部分位于低相对介电常数膜内，并且其中层间绝缘膜，布线，插塞和加强件满足关于 每个层间绝缘膜。

公开(公告)号：US20080164614A1

公开(公告)日：2008-07-10

申请号：US11964336

申请日：2007-12-26

申请人： Sachiyo Ito ,  Masahiko Hasunuma

发明人： Sachiyo Ito ,  Masahiko Hasunuma

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.4 or less respectively, a plurality of wirings provided at least one within each of the interlayer-insulator-film and at least partially located within the low-relative-dielectric-constant-films, a plurality of plugs provided at least one within each of the interlayer-insulator-film and connected to a lower part of the wirings, and a plurality of reinforcement members provided at least one within each of the interlayer-insulator-film with being separated from the wirings at a predetermined interval, electrically cut from the wirings and the plugs, and at least partially located within the low-relative-dielectric-constant-films, and wherein, the interlayer-insulator-films, the wirings, the plugs, and the reinforcement members satisfy a predetermined relation for each of the interlayer-insulator-film.

摘要翻译： 一种半导体器件，包括层叠在衬底上的至少两层层间绝缘膜，并且至少部分由相对介电常数为3.4以下的低相对介电常数膜形成，多个 布线在每个层间绝缘膜内提供至少一个，并且至少部分地位于低相对介电常数膜内;多个插塞，其设置在每个层间绝缘膜内至少一个并连接 连接到布线的下部，以及多个加强构件，其在每个层间绝缘体膜内设置有至少一个在预定间隔内与布线分离的电缆，并从布线和塞子电切割，并且至少 部分位于低相对介电常数膜内，并且其中层间绝缘膜，布线，插塞和加强件满足关于 每个层间绝缘膜。

公开(公告)号：US07301240B2

公开(公告)日：2007-11-27

申请号：US11650935

申请日：2007-01-09

申请人： Masahiko Hasunuma ,  Sachiyo Ito

发明人： Masahiko Hasunuma ,  Sachiyo Ito

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/585 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed, which includes at least two layers superposed on each other in a stacking direction above a substrate, each of the layers including an insulating film a conductive layer films, a conductive plug electrically connected to the conductive layer, and at least one dummy via chain provided in the insulating films and stacked in the at least two layers, wherein the dummy via chain includes at least two reinforcing metal layers and at least one reinforcing plug.

摘要翻译： 公开了一种半导体器件，其包括在衬底上方堆叠方向彼此重叠的至少两个层，每个层包括绝缘膜，导电层膜，与导电层电连接的导电插塞 至少一个虚设通孔链设置在所述绝缘膜中并且堆叠在所述至少两个层中，其中所述虚拟通孔链包括至少两个增强金属层和至少一个增强塞。