公开(公告)号：US09697149B2

公开(公告)日：2017-07-04

申请号：US14027267

申请日：2013-09-16

申请人： Said Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

发明人： Said Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

IPC分类号： G06F13/24 ,  G06F3/06 ,  G06F9/48

CPC分类号： G06F13/24 ,  G06F9/4812 ,  G06F2213/2408

摘要： A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold.

公开(公告)号：US09141546B2

公开(公告)日：2015-09-22

申请号：US13682781

申请日：2012-11-21

申请人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

发明人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

摘要翻译： 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。

公开(公告)号：US20140143487A1

公开(公告)日：2014-05-22

申请号：US13682781

申请日：2012-11-21

申请人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

发明人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

摘要翻译： 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。