-
公开(公告)号：US07202149B2
公开(公告)日：2007-04-10
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译： 通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。 半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有 将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜， 在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上， 其间插入第一绝缘膜和第二绝缘膜。
-
公开(公告)号：US07714367B2
公开(公告)日：2010-05-11
申请号：US11694467
申请日：2007-03-30
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译： 通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。 半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有 将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜， 在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上， 其间插入第一绝缘膜和第二绝缘膜。
-
公开(公告)号：US20070170513A1
公开(公告)日：2007-07-26
申请号：US11694467
申请日：2007-03-30
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译： 通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。 半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有 将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜， 在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上， 其间插入第一绝缘膜和第二绝缘膜。
-
公开(公告)号：US20050133862A1
公开(公告)日：2005-06-23
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/76 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译： 通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。 半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有 将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜， 在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露于第二半导体层上， 其间插入第一绝缘膜和第二绝缘膜。
-
公开(公告)号：US07172931B2
公开(公告)日：2007-02-06
申请号：US10777117
申请日：2004-02-13
IPC分类号： H01L21/84 , H01L21/3205
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78627
摘要： It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristic with high yield. In a method for manufacturing a semiconductor device according to the present invention, a semiconductor layer is formed, a gate insulating film is formed on the semiconductor film, a first conductive layer is formed on the gate insulating film, a second conductive layer is formed on the first conductive layer, the first conductive layer and the second conductive layer are etched to form a first conductive-layer pattern, the second conductive layer in the first conductive-layer pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen to form a second conductive-layer pattern, and a first impurity region and a second impurity region are formed in the semiconductor layer.
摘要翻译： 本发明的目的是提高蚀刻工艺中的选择比，并且提供一种制造具有良好均匀特性且高产率的半导体器件的方法。 在根据本发明的半导体器件的制造方法中，形成半导体层，在半导体膜上形成栅极绝缘膜，在栅极绝缘膜上形成第一导电层，在第二导电层上形成第二导电层 蚀刻第一导电层，第一导电层和第二导电层以形成第一导电层图案，用三氯化硼，氯和氧的等离子体选择性地蚀刻第一导电层图案中的第二导电层， 形成第二导电层图案，并且在半导体层中形成第一杂质区和第二杂质区。
-
公开(公告)号：US07560315B2
公开(公告)日：2009-07-14
申请号：US11438303
申请日：2006-05-23
IPC分类号： H01L21/00 , H01L21/461
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78627
摘要： It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristics with high yield. In a method for manufacturing a semiconductor device according to the present invention, a first layer is formed over a substrate, second layer is formed on the first layer, the first layer and the second layer are etched to form a first pattern, and the second layer in the first pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen using ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) to form a second pattern.
摘要翻译： 本发明的目的是增强蚀刻工艺中的选择比，并提供一种制造具有良好均匀特性且高产率的半导体器件的方法。 在根据本发明的半导体器件的制造方法中，在衬底上形成第一层，在第一层上形成第二层，蚀刻第一层和第二层以形成第一图案，而第二层 使用ECR（电子回旋共振）或ICP（感应耦合等离子体），用三氯化硼，氯和氧的等离子体选择性地蚀刻第一图案中的层以形成第二图案。
-
公开(公告)号：US20070015370A1
公开(公告)日：2007-01-18
申请号：US11438303
申请日：2006-05-23
IPC分类号： H01L21/302
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78627
摘要： It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristics with high yield. In a method for manufacturing a semiconductor device according to the present invention, a semiconductor layer is formed, a gate insulating film is formed on the semiconductor film, a first conductive layer is formed on the gate insulating film, a second conductive layer is formed on the first conductive layer, the first conductive: layer and the second conductive layer are etched to form a first conductive-layer pattern, the second conductive layer in the first conductive-layer pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen to form a second conductive-layer pattern, and a first impurity region and a second impurity region are formed in the semiconductor layer.
摘要翻译： 本发明的目的是增强蚀刻工艺中的选择比，并提供一种制造具有良好均匀特性且高产率的半导体器件的方法。 在根据本发明的半导体器件的制造方法中，形成半导体层，在半导体膜上形成栅极绝缘膜，在栅极绝缘膜上形成第一导电层，在第二导电层上形成第二导电层 第一导电层，第一导电层和第二导电层被蚀刻以形成第一导电层图案，第一导电层图案中的第二导电层被选择性地用三氯化硼，氯和氧的等离子体蚀刻 以形成第二导电层图案，并且在半导体层中形成第一杂质区和第二杂质区。
-
公开(公告)号：US20050181610A1
公开(公告)日：2005-08-18
申请号：US10731089
申请日：2003-12-10
IPC分类号： H01L21/02 , H01L21/28 , H01L21/302 , H01L21/3213 , H01L21/461
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/28123 , H01L21/32136
摘要： [Object] In performing an anisotropic etching process after a taper etching process of a gate conductive layer of a two-layer or three-layer laminated structure, a portion that is not etched is left at an edge of a second conductive film to shorten an LDD region. It is an object to make the LDD region longer by reducing or removing the left portion that is not etched. [Solving Means] After a taper etching process of a gate conductive layer of a two-layer or three-layer laminated structure, an argon plasma treatment is performed. With this argon plasma treatment, a reactive organism in the taper etching process is removed, and it becomes possible to reduce or remove the left portion that is not etched in the anisotropic etching to be performed next.
摘要翻译： 在对二层或三层叠层结构的栅极导电层进行锥蚀刻处理之后进行各向异性蚀刻处理时，未蚀刻的部分留在第二导电膜的边缘以缩短 LDD区域。 本发明的目的是通过减少或去除未蚀刻的左部来使LDD区域更长。 [解决方案]在二层或三层层叠结构的栅极导电层进行锥蚀刻处理之后，进行氩等离子体处理。 通过这种氩等离子体处理，去除了锥形蚀刻工艺中的反应生物体，并且可以减少或去除随后进行的各向异性蚀刻中未被蚀刻的左部分。
-
公开(公告)号：US07485579B2
公开(公告)日：2009-02-03
申请号：US10731089
申请日：2003-12-10
IPC分类号： H01L21/302
CPC分类号： H01L21/02071 , H01L21/28114 , H01L21/28123 , H01L21/32136
摘要： In performing an anisotropic etching process after a taper etching process of a gate conductive layer of a two-layer or three-layer laminated structure, a portion that is not etched is left at an edge of a second conductive film to shorten an LDD region. It is an object to make the LDD region longer by reducing or removing the left portion that is not etched. After a taper etching process of a gate conductive layer of a two-layer or three-layer laminated structure, an argon plasma treatment is performed. With this argon plasma treatment, a reactive organism in the taper etching process is removed, and it becomes possible to reduce or remove the left portion that is not etched in the anisotropic etching to be performed next.
摘要翻译： 在进行两层或三层层叠结构的栅极导电层的锥蚀刻处理后的各向异性蚀刻工艺中，未蚀刻的部分留在第二导电膜的边缘以缩短LDD区域。 本发明的目的是通过减少或去除未蚀刻的左部来使LDD区域更长。 在二层或三层层叠结构的栅极导电层的锥蚀刻工艺之后，进行氩等离子体处理。 通过这种氩等离子体处理，去除了锥形蚀刻工艺中的反应生物体，并且可以减少或去除随后进行的各向异性蚀刻中未被蚀刻的左部分。
-
公开(公告)号：US20070015321A1
公开(公告)日：2007-01-18
申请号：US11524958
申请日：2006-09-22
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L21/32136 , H01L21/32139 , H01L29/42384 , H01L29/78621 , H01L2029/7863
摘要： With respect to the selective ratio in the etching process, it is an object to give design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, by performing an etching process under an etching condition that has a high selective ratio between a mask pattern and metal such as titanium in forming a first conductive layer pattern. A laminated structure comprising a lower first conductive layer and an upper second conductive layer is formed over a semiconductor layer with a gate insulating film interposed therebetween, a mask pattern is formed on the laminated structure, a condition that an etching rate of the mask pattern is fast is used and the second conductive layer and the first conductive layer are etched to form a tapered first conductive layer pattern, and the second conductive layer in the first conductive layer pattern is selectively etched in accordance with the left mask pattern to form a second conductive layer pattern in which a width of the first conductive layer is longer than that of the second conductive layer.
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.025 秒)
