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1.发明授权Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bank 有权只有当所有处理器指示不为该存储器供电时，共享存储器的多处理器系统电源管理才能将存储器供电公开(公告)号：US08112652B2
公开(公告)日：2012-02-07
申请号：US12356274
申请日：2009-01-20
IPC分类号： G06F1/32
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. The hardware power down controller waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.
摘要翻译： 本发明管理多处理器系统中的共享存储器的掉电和唤醒。 每个共享存储器的寄存器具有与每个主器件相对应的位。 当主机要关闭存储器时，它将其相应的位置于寄存器中。 如果任何处理器信号为存储体供电，则存储器组件的硬件掉电控制器为存储体供电。 存储器的硬件掉电控制器只有在所有处理器信号使存储器电源断电的情况下才能关闭存储器。 在启动存储器掉电之前，硬件掉电控制器等待所有主器件在寄存器中设置相应的位。 在任何处理器上运行的软件具有独立于其他处理器的共享存储器的视图，并且不需要处理器间通信。
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公开(公告)号：US20090248991A1
公开(公告)日：2009-10-01
申请号：US12356303
申请日：2009-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.
摘要翻译： 与先前的预取请求相关联的来自CPU到同一存储体的实际请求将与杀死信号一起发送到每存储器存储体逻辑以终止预取请求。 这避免了在将实际请求发送到同一个存储体之前等待预取请求完成。 杀死信号禁止任何完成预取请求的确认。 当对同一存储体中的不同地址的低优先级推测请求已经被分派时，本发明减少了完成高优先级实际请求的等待时间。
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公开(公告)号：US08683133B2
公开(公告)日：2014-03-25
申请号：US12356303
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.
摘要翻译： 与先前的预取请求相关联的来自CPU到同一存储体的实际请求将与杀死信号一起发送到每存储器存储体逻辑以终止预取请求。 这避免了在将实际请求发送到同一个存储体之前等待预取请求完成。 杀死信号禁止任何完成预取请求的确认。 当对同一存储体中的不同地址的低优先级推测请求已经被分派时，本发明减少了完成高优先级实际请求的等待时间。
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公开(公告)号：US20090249105A1
公开(公告)日：2009-10-01
申请号：US12356274
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.
摘要翻译： 本发明管理多处理器系统中的共享存储器的掉电和唤醒。 每个共享存储器的寄存器具有与每个主器件相对应的位。 当主机要关闭存储器时，它将其相应的位置于寄存器中。 如果任何处理器信号为存储体供电，则存储器组件的硬件掉电控制器为存储体供电。 存储器的硬件掉电控制器只有在所有处理器信号使存储器电源断电的情况下才能关闭存储器。 在启动存储器掉电之前，等待所有主机在寄存器中设置相应的位。 在任何处理器上运行的软件具有独立于其他处理器的共享存储器的视图，并且不需要处理器间通信。
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5.发明申请Upgrade of Low Priority Prefetch Requests to High Priority Real Requests in Shared Memory Controller 有权将低优先级预取请求升级到共享内存控制器中的高优先级实时请求公开(公告)号：US20090248992A1
公开(公告)日：2009-10-01
申请号：US12356308
申请日：2009-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.
摘要翻译： 当实际读取访问请求与先前的预取请求相同时，预取控制器实现升级。 响应每存储器存储器逻辑将预取请求的优先级提升为读取请求的优先级。 如果预取请求仍在等待赢得仲裁，则此优先级升级增加了获取访问的可能性通常会降低延迟。 如果预取请求已经通过仲裁获得访问权限，则升级不起作用。 因此，当对相同地址进行低优先级推测预取时，这通常降低了完成高优先级实际请求时的等待时间。
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6.发明授权Upgrade of low priority prefetch requests to high priority real requests in shared memory controller 有权将低优先级预取请求升级到共享内存控制器中的高优先级实际请求公开(公告)号：US08683134B2
公开(公告)日：2014-03-25
申请号：US12356308
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.
摘要翻译： 当实际读取访问请求与先前的预取请求相同时，预取控制器实现升级。 响应每存储器存储器逻辑将预取请求的优先级提升为读取请求的优先级。 如果预取请求仍在等待赢得仲裁，则此优先级升级增加了获取访问的可能性通常会降低延迟。 如果预取请求已经通过仲裁获得访问权限，则升级不起作用。 因此，当对相同地址进行低优先级推测预取时，这通常降低了完成高优先级实际请求时的等待时间。
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公开(公告)号：US08301928B2
公开(公告)日：2012-10-30
申请号：US12356294
申请日：2009-01-20
申请人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
发明人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
IPC分类号： G06F1/00
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.
摘要翻译： 基于硬件的唤醒方案在正常访问掉电存储器时启动内存上电。 触发上电的访问被缓冲。 进一步的访问停止，直到内存完全通电。 然后，缓冲的访问进行到存储器，并且处理器被摆脱失速。 在软件不直接控制访问存储器（例如高速缓存未命中）的情况下，该方案避免了由于访问掉电存储器而导致的不期望的状况。
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公开(公告)号：US20090249106A1
公开(公告)日：2009-10-01
申请号：US12356294
申请日：2009-01-20
申请人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
发明人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.
摘要翻译： 基于硬件的唤醒方案在正常访问掉电存储器时启动内存上电。 触发上电的访问被缓冲。 进一步的访问停止，直到内存完全通电。 然后，缓冲的访问进行到存储器，并且处理器被摆脱失速。 在软件不直接控制访问存储器（例如高速缓存未命中）的情况下，该方案避免了由于访问掉电存储器而导致的不期望的状况。
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公开(公告)号：US08078897B2
公开(公告)日：2011-12-13
申请号：US12356286
申请日：2009-01-20
申请人： Sajish Sajayan , Alok Anand , Sudhakar Surendran
发明人： Sajish Sajayan , Alok Anand , Sudhakar Surendran
IPC分类号： G06F1/26
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down.
摘要翻译： 本发明是用于共享存储器多处理器系统的功率管理方案，其在主专用逻辑和存储体逻辑之间分离控制逻辑。 从中央掉电控制器启动掉电。 该中央掉电控制器通知主机和目标特定逻辑。 进一步的内存访问被阻止。 所有待处理的活动完成 然后，中央控制器继续关闭存储器并通知主设备，并在完成后指定特定逻辑。 从接收到掉电请求到掉电完成的时间之后，主机专用逻辑不会启动唤醒请求。
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10.发明授权Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler 有权用于使用设计编译器进行多电压优化的异步时钟域边界层次分离的方法公开(公告)号：US07945875B2
公开(公告)日：2011-05-17
申请号：US12137835
申请日：2008-06-12
申请人： Alok Anand , Sajish Sajayan
发明人： Alok Anand , Sajish Sajayan
CPC分类号： G06F17/5059 , G06F2217/08 , G06F2217/78
摘要： This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.
摘要翻译： 本发明使用涉及寄存器分组，逻辑修改和电平移位器以及隔离单元插入的流程在异步时钟边界处转换电路设计。 测试插入的电平移位器和隔离单元的位置。 变换电路设计适用于独立控制单独电压域的功耗控制。
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