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公开(公告)号：US11908417B2
公开(公告)日：2024-02-20
申请号：US17728584
申请日：2022-04-25
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
CPC classification number: G09G3/3266 , G09G3/20 , G09G3/3677 , G11C19/28 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US11315495B2
公开(公告)日：2022-04-26
申请号：US15488259
申请日：2017-04-14
Applicant: Samsung Display Co., Ltd.
Inventor： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US09613582B2
公开(公告)日：2017-04-04
申请号：US14340396
申请日：2014-07-24
Applicant: Samsung Display Co., Ltd.
Inventor： Sung Man Kim , Jun Ho Song , Beom Jun Kim , Seong Yeol Syn , Young Je Cho
CPC classification number: G09G3/3677 , G09G2300/0413 , G09G2310/0286 , G09G2320/041 , G11C19/28
Abstract: Provided is a gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines. The stage includes a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to a output terminal of a present stage and an input terminal connected to a first clock terminal, a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, and a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to the first node, and an output terminal connected to the buffer node.
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公开(公告)号：US12027097B2
公开(公告)日：2024-07-02
申请号：US18135212
申请日：2023-04-17
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
CPC classification number: G09G3/2092 , G09G3/3648 , G09G3/3677 , G11C19/28 , G09G2300/0809 , G09G2310/0286
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US11645955B2
公开(公告)日：2023-05-09
申请号：US17468089
申请日：2021-09-07
Applicant: Samsung Display Co., LTD.
Inventor： Seung-Kyu Lee , Sang Seop Kum , Beom Jun Kim
CPC classification number: G09F9/3026 , G06F3/1446
Abstract: A display panel alignment device of a tiling display includes a frame including panel seating portions and a gap around the panel seating portions, and a panel movement controller disposed in each of the panel seating portions. A display panel is disposed in each of the panel seating portions. The panel movement controller controls a movement of the display panel in a front direction, a rear direction, a left direction, and a right direction, and controls rotation of the display panel.
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Patent Agency Ranking
公开(公告)号：US09865212B2
公开(公告)日：2018-01-09
申请号：US14742915
申请日：2015-06-18
Applicant: Samsung Display Co., Ltd.
Inventor： Duc-Han Cho , Kang Nam Kim , Beom Jun Kim , You Mee Hyun
CPC classification number: G09G3/3677 , G09G3/3648 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.
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公开(公告)号：US10957242B2
公开(公告)日：2021-03-23
申请号：US16583018
申请日：2019-09-25
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US10467946B2
公开(公告)日：2019-11-05
申请号：US15417092
申请日：2017-01-26
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US20180018920A1
公开(公告)日：2018-01-18
申请号：US15488259
申请日：2017-04-14
Applicant: Samsung Display Co., Ltd.
Inventor： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G09G3/36
CPC classification number: G09G3/3266 , G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US11631359B2
公开(公告)日：2023-04-18
申请号：US17209068
申请日：2021-03-22
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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