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公开(公告)号：US11908417B2
公开(公告)日：2024-02-20
申请号：US17728584
申请日：2022-04-25
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
CPC classification number: G09G3/3266 , G09G3/20 , G09G3/3677 , G11C19/28 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US11315495B2
公开(公告)日：2022-04-26
申请号：US15488259
申请日：2017-04-14
Applicant: Samsung Display Co., Ltd.
Inventor： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US09203395B2
公开(公告)日：2015-12-01
申请号：US13929937
申请日：2013-06-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kang Nam Kim , Duc-Han Cho , You Mee Hyun , Jeong-Il Kim , Jong Woong Chang
CPC classification number: H03K17/145 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041
Abstract: A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.
Abstract translation: 栅极驱动器包括多个级，其中第n级包括：上拉单元，被配置为输出时钟信号的高电压作为第n门信号的高电压; 下拉单元，被配置为将第n栅极信号的高电压降低到第一低电压; 放电单元，被配置为将所述第一节点的电压放电到低于所述第一低电压的第二低电压; 输入单元，被配置为输出所述时钟信号的高电压作为第n进位信号; 逆变器单元，被配置为与时钟信号同步地输出信号; 第一节点存储单元，被配置为将所述第一节点的电压维持在所述第二低电压; 以及第二节点存储单元，被配置为将所述第二节点的电压维持在所述第一或第二低电压。
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公开(公告)号：US11631359B2
公开(公告)日：2023-04-18
申请号：US17209068
申请日：2021-03-22
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US09589519B2
公开(公告)日：2017-03-07
申请号：US14203272
申请日：2014-03-10
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
CPC classification number: G09G3/2092 , G09G3/3648 , G09G3/3677 , G09G2300/0809 , G09G2310/0286 , G11C19/28
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
Abstract translation: 提供显示面板。 显示面板包括包括栅线和数据线的显示区域，以及连接到栅极线的端子的栅极驱动器。 栅极驱动器包括集成在衬底上的多个级，并且每个级包括逆变器单元，输出单元和Q结点稳定单元。 输出单元包括第一晶体管和第一电容器，其中第一晶体管包括用于接收时钟信号的输入端子，连接到节点Q的控制端子和连接到栅极电压输出端子的输出端子以输出栅极 电压。 当输出单元输出栅极导通电压时，Q节点稳定单元中的晶体管的Vgs电压具有等于或小于0V的值。
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Patent Agency Ranking
公开(公告)号：US10957242B2
公开(公告)日：2021-03-23
申请号：US16583018
申请日：2019-09-25
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US10467946B2
公开(公告)日：2019-11-05
申请号：US15417092
申请日：2017-01-26
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US20180018920A1
公开(公告)日：2018-01-18
申请号：US15488259
申请日：2017-04-14
Applicant: Samsung Display Co., Ltd.
Inventor： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G09G3/36
CPC classification number: G09G3/3266 , G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US12027097B2
公开(公告)日：2024-07-02
申请号：US18135212
申请日：2023-04-17
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
CPC classification number: G09G3/2092 , G09G3/3648 , G09G3/3677 , G11C19/28 , G09G2300/0809 , G09G2310/0286
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US09865212B2
公开(公告)日：2018-01-09
申请号：US14742915
申请日：2015-06-18
Applicant: Samsung Display Co., Ltd.
Inventor： Duc-Han Cho , Kang Nam Kim , Beom Jun Kim , You Mee Hyun
CPC classification number: G09G3/3677 , G09G3/3648 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.
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