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公开(公告)号：US09515091B2
公开(公告)日：2016-12-06
申请号：US14099977
申请日：2013-12-08
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Bon-Yong Koo , Soo Jin Park , Jong-Moon Park , Yong Hee Lee , Jong-Hyuk Lee , Duc-Han Cho
IPC: H01L29/04 , H01L27/12 , H01L29/417 , H01L27/15
CPC classification number: H01L29/41733 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L29/41775
Abstract: A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.
Abstract translation: 薄膜晶体管阵列面板包括在延伸方向上延伸的栅极线，并且包括从其延伸的栅极和虚拟栅电极; 源电极和在其第一端包括漏极的单个漏极构件和在其相对的第二端处的虚设漏电极。 漏电极相对于栅电极面对源电极，虚设漏电极与虚拟栅电极重叠。 漏极和虚设漏电极分别包括在延伸方向上具有预定宽度的多个第一和第二区域。 第二区域包括与延伸方向形成约0度至约90度的角度的边缘，并且多个第二区域中的至少一个的平面区域与剩余的第二区域的平面区域不同。
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公开(公告)号：US09218074B2
公开(公告)日：2015-12-22
申请号：US13719488
申请日：2012-12-19
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Duc-Han Cho , Kang-Nam Kim , Jae-Hoon Lee , You-Mee Hyun , Jong-Woong Chang , Yun Heo
CPC classification number: G06F3/038 , G09G3/3674 , G09G5/001 , G09G2310/0286 , G11C19/28 , H03K3/00
Abstract: A gate drive circuit in which multiple stages are connected together one after each other. An n-th stage includes a pull-up part, a carry part, a pull-down part, a switching part, a first maintaining part and a second maintaining part. The pull-up part outputs a high voltage of a first clock signal. The carry part outputs a high voltage of the first clock signal. The pull-down part pulls-down the n-th gate signal into a first low voltage. The switching part outputs a first signal synchronized with the first clock signal during an interval other than a high voltage output interval of the n-th carry signal. The first maintaining part maintains the n-th gate signal at the first low voltage in response to the first signal. The second maintaining part maintains the n-th gate signal at the first low voltage in response to a second signal.
Abstract translation: 一个栅极驱动电路，其中多个级彼此连接在一起。 第n级包括上拉部分，进位部分，下拉部分，切换部分，第一维持部分和第二维持部分。 上拉部分输出第一时钟信号的高电压。 进位部分输出第一时钟信号的高电压。 下拉部分将第n个门信号下拉到第一个低电压。 开关部分在与第n个进位信号的高电压输出间隔之外的间隔期间输出与第一时钟信号同步的第一信号。 第一维持部分响应于第一信号将第n个栅极信号保持在第一低电压。 第二维持部分响应于第二信号将第n个门信号保持在第一低电压。
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公开(公告)号：US09203395B2
公开(公告)日：2015-12-01
申请号：US13929937
申请日：2013-06-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kang Nam Kim , Duc-Han Cho , You Mee Hyun , Jeong-Il Kim , Jong Woong Chang
CPC classification number: H03K17/145 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041
Abstract: A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.
Abstract translation: 栅极驱动器包括多个级，其中第n级包括：上拉单元，被配置为输出时钟信号的高电压作为第n门信号的高电压; 下拉单元，被配置为将第n栅极信号的高电压降低到第一低电压; 放电单元，被配置为将所述第一节点的电压放电到低于所述第一低电压的第二低电压; 输入单元，被配置为输出所述时钟信号的高电压作为第n进位信号; 逆变器单元，被配置为与时钟信号同步地输出信号; 第一节点存储单元，被配置为将所述第一节点的电压维持在所述第二低电压; 以及第二节点存储单元，被配置为将所述第二节点的电压维持在所述第一或第二低电压。
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Patent Agency Ranking
公开(公告)号：US09780177B2
公开(公告)日：2017-10-03
申请号：US15369008
申请日：2016-12-05
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan Hwang , Bon-Yong Koo , Soo Jin Park , Jong-Moon Park , Yong Hee Lee , Jong-Hyuk Lee , Duc-Han Cho
IPC: H01L29/04 , H01L29/417 , H01L27/12 , H01L27/15
CPC classification number: H01L29/41733 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L29/41775
Abstract: A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.
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公开(公告)号：US09978327B2
公开(公告)日：2018-05-22
申请号：US14973766
申请日：2015-12-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Duc-Han Cho , Beomjun Kim , Yoonho Kim , Noboru Takeuchi , Kangnam Kim
CPC classification number: G09G3/3677 , G09G3/3614 , G11C19/184 , G11C19/28
Abstract: A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.
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6.发明申请公开(公告)号：US20160210928A1
公开(公告)日：2016-07-21
申请号：US14973766
申请日：2015-12-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Duc-Han Cho , Beomjun Kim , Yoonho Kim , Noboru Takeuchi , Kangnam Kim
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3614 , G11C19/184 , G11C19/28
Abstract: A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.
Abstract translation: 门驱动电路包括驱动级。 每个驱动级将每个栅极信号施加到显示面板的每个栅极线。 第k（k是等于或大于2的自然数）驱动级包括第一输出晶体管，电容器以及第一和第二控制晶体管。 第一输出晶体管包括连接到第一节点的控制电极，接收时钟信号的输入电极和输出第k个门信号的输出电极。 电容器连接在第一输出晶体管的输出电极和第一输出晶体管的控制电极之间。 第一控制晶体管将第一控制信号施加到第二节点，以在输出第k个门信号之前控制第一节点的电压。 第二控制晶体管二极管连接在第二节点和第一节点之间。
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公开(公告)号：US09865212B2
公开(公告)日：2018-01-09
申请号：US14742915
申请日：2015-06-18
Applicant: Samsung Display Co., Ltd.
Inventor： Duc-Han Cho , Kang Nam Kim , Beom Jun Kim , You Mee Hyun
CPC classification number: G09G3/3677 , G09G3/3648 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.
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公开(公告)号：US20140204009A1
公开(公告)日：2014-07-24
申请号：US13929937
申请日：2013-06-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kang Nam Kim , Duc-Han Cho , You Mee Hyun , Jeong-II Kim , Jong Woong Chang
CPC classification number: H03K17/145 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041
Abstract: A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.
Abstract translation: 栅极驱动器包括多个级，其中第n级包括：上拉单元，被配置为输出时钟信号的高电压作为第n门信号的高电压; 下拉单元，被配置为将第n栅极信号的高电压降低到第一低电压; 放电单元，被配置为将所述第一节点的电压放电到低于所述第一低电压的第二低电压; 输入单元，被配置为输出所述时钟信号的高电压作为第n进位信号; 逆变器单元，被配置为与时钟信号同步地输出信号; 第一节点存储单元，被配置为将所述第一节点的电压维持在所述第二低电压; 以及第二节点存储单元，被配置为将所述第二节点的电压维持在所述第一或第二低电压。
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