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公开(公告)号:US11908417B2
公开(公告)日:2024-02-20
申请号:US17728584
申请日:2022-04-25
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
CPC classification number: G09G3/3266 , G09G3/20 , G09G3/3677 , G11C19/28 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号:US12080238B2
公开(公告)日:2024-09-03
申请号:US18223459
申请日:2023-07-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Yoon Jung Chai , Won Jun Lee , Chol Ho Kim , Sung Hoon Lim , Yoo Seok Jang
IPC: G09G3/3233 , G09G3/20 , G09G3/3266
CPC classification number: G09G3/3233 , G09G3/3266 , G09G3/2007 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2310/0294 , G09G2310/08 , G09G2320/0252
Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.
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公开(公告)号:US12002404B2
公开(公告)日:2024-06-04
申请号:US18132704
申请日:2023-04-10
Applicant: Samsung Display Co., Ltd.
Inventor: Kang Nam Kim , Sung Hoon Lim , Woo Geun Lee , Kyu Sik Cho , Jae Beom Choi
IPC: G09G3/20 , G09G3/3266 , G09G3/3233
CPC classification number: G09G3/2092 , G09G3/3233 , G09G3/3266 , G09G2310/0202 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/08
Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
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公开(公告)号:US11521570B2
公开(公告)日:2022-12-06
申请号:US16809452
申请日:2020-03-04
Applicant: Samsung Display Co., Ltd.
Inventor: Sung Hoon Lim , Kang Nam Kim , Seok Hwan Bang , Sung Hwan Won , Woo Geun Lee , Kyu Sik Cho , Soo Jung Chae
IPC: G09G3/36
Abstract: A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.
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公开(公告)号:US11315495B2
公开(公告)日:2022-04-26
申请号:US15488259
申请日:2017-04-14
Applicant: Samsung Display Co., Ltd.
Inventor: Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号:US11626060B2
公开(公告)日:2023-04-11
申请号:US17478825
申请日:2021-09-17
Applicant: Samsung Display Co., Ltd.
Inventor: Kang Nam Kim , Sung Hoon Lim , Woo Geun Lee , Kyu Sik Cho , Jae Beom Choi
IPC: G09G3/3266 , G09G3/20
Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
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公开(公告)号:US09559210B2
公开(公告)日:2017-01-31
申请号:US14800187
申请日:2015-07-15
Applicant: Samsung Display Co. Ltd.
Inventor: Dong Gun Oh , Young Gu Kang , Sung In Ro , Jae Hak Lee , Sung Hoon Lim , Woong Ki Jeon
IPC: H01L29/786 , H01L29/66 , H01L27/12
CPC classification number: H01L27/124 , H01L27/1214 , H01L27/1248 , H01L27/1259 , H01L27/1262 , H01L29/66742 , H01L29/78648 , H01L29/78669 , H01L29/78678 , H01L29/7869
Abstract: A thin film transistor is provided as follows. A first gate electrode and a second gate electrode are stacked on each other. A semiconductor layer is interposed between the first and second gate electrodes. A source electrode and a drain electrode are interposed between the semiconductor layer and the second gate electrode. A connection electrode connects electrically the first gate electrode and the second gate electrode. A first insulating film is interposed between the first gate electrode and the semiconductor layer. A second insulating film includes a first part interposed between the semiconductor layer and the second gate electrode and a second part interposed between the second gate electrode and the drain electrode. A third insulating film includes a first part interposed between the connection electrode and the second gate electrode.
Abstract translation: 如下提供薄膜晶体管。 第一栅电极和第二栅电极彼此堆叠。 半导体层介于第一和第二栅电极之间。 源电极和漏电极插入在半导体层和第二栅电极之间。 连接电极电连接第一栅电极和第二栅电极。 第一绝缘膜介于第一栅电极和半导体层之间。 第二绝缘膜包括插入在半导体层和第二栅电极之间的第一部分和介于第二栅电极和漏电极之间的第二部分。 第三绝缘膜包括插入在连接电极和第二栅电极之间的第一部分。
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公开(公告)号:US10303027B2
公开(公告)日:2019-05-28
申请号:US15483749
申请日:2017-04-10
Applicant: Samsung Display Co., Ltd
Inventor: Duk Sung Kim , Seung Hyun Park , Jun Ho Song , Sung Hoon Lim
IPC: G02F1/136 , G02F1/1368 , G02F1/1333 , G02F1/1343 , G02F1/1362
Abstract: A liquid crystal display device comprising: a substrate; a gate line that is disposed on the substrate and extends in a first direction; a first insulating film that is disposed on the gate line; a semiconductor pattern that is disposed on the first insulating film; a first transparent electrode that is disposed on the semiconductor pattern, and has a first electrode and a second electrode being spaced apart from each other; a second insulating film that is disposed on the first transparent electrode and partially exposes the first electrode; a data line disposed on the second insulating film and extends in a second direction different from the first direction; a second transparent electrode that is disposed on the second insulating film and at least partially overlaps the second electrode; and a connecting electrode in direct contact with a portion of the exposed first electrode and the data line.
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公开(公告)号:US10295874B2
公开(公告)日:2019-05-21
申请号:US15395503
申请日:2016-12-30
Applicant: Samsung Display Co., Ltd.
Inventor: Dong Gun Oh , Sung Hoon Lim , Do Hyun Jung , Jean Ho Song , Hyeon Jun Lee
IPC: G02F1/1362 , G02F1/1333 , G02F1/1343 , G02F1/1368 , G02F1/1345
Abstract: A display device may include a switching device, a gate line, a data line, a pixel electrode, and an auxiliary line. The switching device includes a first electrode, a second electrode, and a third electrode. The gate line is electrically connected to the first electrode. The data line crosses the gate line in a plan view of the display device and is electrically connected to the second electrode. The pixel electrode is electrically connected to the third electrode. The auxiliary line is electrically connected through the first gate line to the first electrode and crosses the gate line in the plan view of the display device.
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公开(公告)号:US20180018920A1
公开(公告)日:2018-01-18
申请号:US15488259
申请日:2017-04-14
Applicant: Samsung Display Co., Ltd.
Inventor: Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC: G09G3/36
CPC classification number: G09G3/3266 , G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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