公开(公告)号：US20170053585A1

公开(公告)日：2017-02-23

申请号：US15054580

申请日：2016-02-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： YOUNG-SOO SOHN ,  NEUNG-BEOM LEE ,  JEONG-HYUN KIM ,  JIN-SEUK KIM ,  WON-HEE LEE

IPC: G09G3/20

CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G2310/0248 ,  G09G2310/0267

Abstract: A gate driver includes a first shift-register including a plurality of odd-numbered stages which outputs a plurality of odd-numbered original gate signals having a pre-charge pulse and a main-charge pulse in synchronization with a first gate clock signal, a second shift-register comprising a plurality of even-numbered stages which outputs a plurality of even-numbered original gate signals having a pre-charge pulse and a main-charge pulse in synchronization with a second gate clock signal, a first inverter configured to output a first inversion pre-charge control signal having a phase opposite to a phase of a first pre-charge control signal, and a second inverter configured to output a second inversion pre-charge control signal having a phase opposite to a phase of a second pre-charge control signal.

Abstract translation: 栅极驱动器包括：第一移位寄存器，包括多个奇数级，其与第一栅极时钟信号同步地输出具有预充电脉冲和主充电脉冲的多个奇数原始栅极信号; 第二移位寄存器，包括多个偶数级，其输出具有与第二栅极时钟信号同步的预充电脉冲和主充电脉冲的多个偶数原始门信号，第一反相器被配置为输出 第一反相预充电控制信号，其具有与第一预充电控制信号的相位相反的相位;以及第二反相器，被配置为输出具有与第二预充电控制信号的相位相反的相位的第二反相预充电控制信号 充电控制信号。

公开(公告)号：US20180137804A1

公开(公告)日：2018-05-17

申请号：US15806555

申请日：2017-11-08

Applicant: Samsung Display Co., Ltd.

Inventor： MIN-SOO CHOI ,  JUNPYO LEE ,  YU-CHOL KIM ,  JEONG-HYUN KIM

IPC: G09G3/20

Abstract: A display apparatus includes a gate driving control circuit, a gate driver and a display panel. The gate driving control circuit generates N gate clock signals and N inversion gate clock signals based on N gate clock control signals, phases of which partially overlap with each other. Each inversion gate clock signals has an opposite phase to a respective gate clock signal. The gate driver generates gate signals based on the N gate clock signals or the N inversion gate clock signals and applies the gate signals to gate lines. The display panel includes pixels, each connected to a respective gate line and a respective data line. Each of the pixels has a longer side in parallel with gate lines and a shorter side in parallel with the data lines. A number of the gate clock control signals is an integer multiple of a number of colors of the pixels.

公开(公告)号：US20170148397A1

公开(公告)日：2017-05-25

申请号：US15179080

申请日：2016-06-10

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： WOONYONG LIM ,  KYEONGSEOK LEE ,  JAEHYUN KOH ,  SUNG-JUN KIM ,  JEONG-HYUN KIM ,  SUNGSOO CHOI

IPC: G09G3/36

CPC classification number: G09G3/3607 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3685 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0242

Abstract: A display apparatus includes a display panel, a timing controller and a data driver. The display panel includes a data line and first and second pixels connected to the data line. The timing controller generates a data signal and a data kickback control signal in response to input image data. The data driver generates first and second data voltages in response to the data signal, generates a data kickback signal in response to the data kickback control signal, processes the data voltages and the data kickback signal, and outputs the first data voltage to the data line during a first duration, the second data voltage to the data line during a second duration, and a first kickback data voltage to the data line during a first data kickback duration. The first data kickback duration is between the first and second durations.