公开(公告)号：US11514832B2

公开(公告)日：2022-11-29

申请号：US17374893

申请日：2021-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： Sooyeon Kim ,  Taegon Im ,  Jihyun Kim ,  Jiye Lee

IPC: G09G3/20

Abstract: A display apparatus includes a display panel, a gamma reference voltage generator and a data driver. The gamma reference voltage generator is configured to generate a gamma reference voltage. The gamma reference voltage includes a gamma amplifier configured to output the gamma reference voltage. The data driver is configured to generate a data voltage based on the gamma reference voltage and to output the data voltage to the display panel. A polarity of an offset voltage of the gamma amplifier is inverted alternately in a unit of one frame and in a unit of two frames.

公开(公告)号：US20170206847A1

公开(公告)日：2017-07-20

申请号：US15365292

申请日：2016-11-30

Applicant: Samsung Display Co., Ltd.

Inventor： Yoonsik Park ,  Kyunho Kim ,  Yu-chol Kim ,  Jongjae Lee ,  Jiye Lee ,  Youngsuk Jung ,  Hyehyun Jeong

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G3/3688 ,  G09G5/18 ,  G09G2310/08 ,  G09G2330/025 ,  G09G2330/04 ,  G09G2330/12

Abstract: A clock generation circuit includes: a clock generator to receive a gate pulse signal and to generate at least one gate clock signal corresponding to the gate pulse signal; an over-current protector to detect a current level of the at least one gate clock signal, and to output a shutdown enable signal and at least one switching signal corresponding to the detected current level; and a switching unit including at least one switching device to output the gate pulse signal as the at least one gate clock signal. The clock generator is to generate the at least one gate clock signal in response to the shutdown enable signal, and the at least one switching device is to transmit the gate pulse signal as the at least one gate clock signal in response to the at least one switching signal.

公开(公告)号：US20220093025A1

公开(公告)日：2022-03-24

申请号：US17374893

申请日：2021-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： SOOYEON KIM ,  Taegon Im ,  Jihyun Kim ,  Jiye Lee

IPC: G09G3/20

Abstract: A display apparatus includes a display panel, a gamma reference voltage generator and a data driver. The gamma reference voltage generator is configured to generate a gamma reference voltage. The gamma reference voltage includes a gamma amplifier configured to output the gamma reference voltage. The data driver is configured to generate a data voltage based on the gamma reference voltage and to output the data voltage to the display panel. A polarity of an offset voltage of the gamma amplifier is inverted alternately in a unit of one frame and in a unit of two frames.

公开(公告)号：US12027094B2

公开(公告)日：2024-07-02

申请号：US17115838

申请日：2020-12-09

Applicant: Samsung Display Co., Ltd.

Inventor： Sooyeon Kim ,  Hee-Jeong Seo ,  Jiye Lee ,  Taegon Im ,  Junghwan Cho

IPC: G09G3/3275 ,  G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/027 ,  G09G2310/0275

Abstract: Provided is a data driver including a digital to analog converter configured to convert image signal data into a plurality of data voltages, and an output buffer unit including a plurality of channels for outputting the plurality of data voltages. The output buffer unit includes a plurality of output blocks. Each output block includes one or more channels. Data voltages outputted from a first output block among the plurality of output blocks are delayed with a first time difference. Data voltages outputted from a second output block among the plurality of output blocks are delayed with a second time difference which is different from the first time difference.

公开(公告)号：US10325564B2

公开(公告)日：2019-06-18

申请号：US15365292

申请日：2016-11-30

Applicant: Samsung Display Co., Ltd.

Inventor： Yoonsik Park ,  Kyunho Kim ,  Yu-chol Kim ,  Jongjae Lee ,  Jiye Lee ,  Youngsuk Jung ,  Hyehyun Jeong

IPC: G09G3/36

Abstract: A clock generation circuit includes: a clock generator to receive a gate pulse signal and to generate at least one gate clock signal corresponding to the gate pulse signal; an over-current protector to detect a current level of the at least one gate clock signal, and to output a shutdown enable signal and at least one switching signal corresponding to the detected current level; and a switching unit including at least one switching device to output the gate pulse signal as the at least one gate clock signal. The clock generator is to generate the at least one gate clock signal in response to the shutdown enable signal, and the at least one switching device is to transmit the gate pulse signal as the at least one gate clock signal in response to the at least one switching signal.