公开(公告)号：US09893203B2

公开(公告)日：2018-02-13

申请号：US15246366

申请日：2016-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Seok Hwan Bang ,  Sook-Hwan Ban ,  Hyung Jun Kim ,  Woo Geun Lee ,  Hyeon Jun Lee

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/32 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L29/7869 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78696

Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.