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公开(公告)号：US10862667B2
公开(公告)日：2020-12-08
申请号：US16817372
申请日：2020-03-12
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon
Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
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公开(公告)号：US20220109555A1
公开(公告)日：2022-04-07
申请号：US17553546
申请日：2021-12-16
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon
Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
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公开(公告)号：US11206124B2
公开(公告)日：2021-12-21
申请号：US17108970
申请日：2020-12-01
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon
Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
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公开(公告)号：US11711199B2
公开(公告)日：2023-07-25
申请号：US17553546
申请日：2021-12-16
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon
CPC classification number: H04L7/0337 , H03L7/0805 , H03L7/087
Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
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公开(公告)号：US20190280591A1
公开(公告)日：2019-09-12
申请号：US16109645
申请日：2018-08-22
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon , Amir Amirkhany , Anup P. Jose
Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
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Patent Agency Ranking
公开(公告)号：US20190265278A1
公开(公告)日：2019-08-29
申请号：US16054609
申请日：2018-08-03
Applicant: Samsung Display Co., Ltd.
Inventor： Da Wei , Mohammad Hekmat , Valentin Abramzon , Amir Amirkhany
Abstract: An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.
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公开(公告)号：US10444785B2
公开(公告)日：2019-10-15
申请号：US16109656
申请日：2018-08-22
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon
Abstract: A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.
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公开(公告)号：US20190286186A1
公开(公告)日：2019-09-19
申请号：US16109656
申请日：2018-08-22
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon
Abstract: A system and method quadrature clock generation circuit includes an approximate quadrature clock generator and an I/Q correction circuit. The approximate quadrature clock generator has an input configured to receive an input signal and generate an approximate quadrature clock and an approximate in-phase clock using the input signal. The I/Q correction circuit is configured to receive the approximate quadrature clock at a first quadrature input and the approximate in-phase clock at a first in-phase input and output an improved quadrature clock at a first quadrature output and improved in-phase clock at a first in-phase output.
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公开(公告)号：US20190286178A1
公开(公告)日：2019-09-19
申请号：US16057124
申请日：2018-08-07
Applicant: Samsung Display Co., Ltd.
Inventor： Da Wei , Valentin Abramzon
IPC: G05F1/445 , H03K3/0233 , G09G3/00
Abstract: A comparator. The comparator includes two back-to-back inverters, a differential pair, and a first common mode compensation transistor. The differential pair has two outputs configured to receive respective series currents from, or supply respective series currents to, the back-to-back inverters. The first common mode compensation transistor is configured to supply a compensating current to, or draw a compensating current from, a first output of the two outputs of the differential pair.
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公开(公告)号：US10411593B1
公开(公告)日：2019-09-10
申请号：US16109645
申请日：2018-08-22
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon , Amir Amirkhany , Anup P. Jose
Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
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