公开(公告)号：US12176328B2

公开(公告)日：2024-12-24

申请号：US18447535

申请日：2023-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho Lee ,  Kilsoo Kim

IPC: H01L25/10 ,  H01L23/538

Abstract: A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.

公开(公告)号：US11769762B2

公开(公告)日：2023-09-26

申请号：US17160878

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho Lee ,  Kilsoo Kim

IPC: H01L25/10 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L2225/1047

Abstract: A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.

公开(公告)号：US20220285328A1

公开(公告)日：2022-09-08

申请号：US17648424

申请日：2022-01-20

Applicant: Samsung Electronics Co., LTD

Inventor： DONGKYU KIM ,  Daeho Lee ,  Seokhyun Lee ,  Minjung Kim ,  Taewon Yoo

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.

公开(公告)号：US12237319B2

公开(公告)日：2025-02-25

申请号：US18418964

申请日：2024-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho Lee ,  Taeje Cho

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065

Abstract: A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.

公开(公告)号：US12062647B2

公开(公告)日：2024-08-13

申请号：US17457660

申请日：2021-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeho Lee ,  Jinhyun Kim ,  Wansoo Park

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip disposed on the first redistribution substrate, a first mold layer that covers the first semiconductor chip and the first redistribution substrate, a second redistribution substrate disposed on the first mold layer, a second semiconductor chip disposed on the second redistribution substrate, where the second semiconductor chip includes a second-chip first conductive bump that does not overlap the first semiconductor chip, a first sidewall that overlaps the first semiconductor chip, and a second sidewall that does not overlap the first semiconductor chip, wherein the first sidewall and the second sidewall are opposite to each other, and a first mold via that penetrates the first mold layer connects the second-chip first conductive bump to the first redistribution substrate, and overlaps the second-chip first conductive bump.

公开(公告)号：US11923351B2

公开(公告)日：2024-03-05

申请号：US17368028

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho Lee ,  Taeje Cho

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.