公开(公告)号：US20190280081A1

公开(公告)日：2019-09-12

申请号：US16424996

申请日：2019-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Hun CHOI ,  Young Tak KIM ,  Da Il EOM ,  Sun Jung LEE

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.

公开(公告)号：US20240135147A1

公开(公告)日：2024-04-25

申请号：US18450839

申请日：2023-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Jung Ho AHN ,  Sun Jung LEE ,  Jae Wan CHOI

IPC: G06N3/0455

CPC classification number: G06N3/0455

Abstract: A device including processors configured to execute instructions and memories storing the instructions, which when executed by the processors configure the processors to perform an operation for training a transformer model having a plurality of encoders and a plurality of decoders by configuring the processors to identify the batches of training data into a plurality of micro-batches, select layer pairs for the plurality of micro-batches, assemble a processing order of the layer pairs, determining resource information to be allocated to the layer pairs, and allocate resources to the layer pairs based on the determined resource information to be allocated to the layer pairs, dependent con the processing order of the layer pairs.

公开(公告)号：US20240153948A1

公开(公告)日：2024-05-09

申请号：US18415863

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5283 ,  H01L29/42364 ,  H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US20250113597A1

公开(公告)日：2025-04-03

申请号：US18978581

申请日：2024-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L27/092 ,  H01L29/423 ,  H01L29/739

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US20240232581A9

公开(公告)日：2024-07-11

申请号：US18450839

申请日：2023-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Jung Ho AHN ,  Sun Jung LEE ,  Jae Wan CHOI

IPC: G06N3/0455

CPC classification number: G06N3/0455

Abstract: A device including processors configured to execute instructions and memories storing the instructions, which when executed by the processors configure the processors to perform an operation for training a transformer model having a plurality of encoders and a plurality of decoders by configuring the processors to identify the batches of training data into a plurality of micro-batches, select layer pairs for the plurality of micro-batches, assemble a processing order of the layer pairs, determining resource information to be allocated to the layer pairs, and allocate resources to the layer pairs based on the determined resource information to be allocated to the layer pairs, dependent con the processing order of the layer pairs.

公开(公告)号：US20240184630A1

公开(公告)日：2024-06-06

申请号：US18526603

申请日：2023-12-01

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Jung Ho AHN ,  Sun Jung LEE ,  Jae Wan CHOI ,  Seung Hwan HWANG

IPC: G06F9/50 ,  G06F5/01 ,  G06F15/80

CPC classification number: G06F9/5027 ,  G06F5/01 ,  G06F15/8046

Abstract: A device and method with batch normalization are provided. An accelerator includes: core modules, each core module including a respective plurality of cores configured to perform a first convolution operation using feature map data and a weight; local reduction operation modules adjacent to the respective core modules, each including a respective plurality of local reduction operators configured to perform a first local operation that obtains first local statistical values of the corresponding core module; a global reduction operation module configured to perform a first global operation that generates first global statistical values of the core module based on the first local statistical values of the core modules; and a normalization operation module configured to perform a first normalization operation on the feature map data based on the first global statistical values.

公开(公告)号：US20180314417A1

公开(公告)日：2018-11-01

申请号：US15966990

申请日：2018-04-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Young Seok LIM ,  Hong Seok KWON ,  Ho Min MOON ,  Mi Jung PARK ,  Woo Young PARK ,  Ki Hyoung SON ,  Won Ick AHN ,  Pil Seung YANG ,  Jae Seok YOON ,  Gi Soo LEE ,  Sun Jung LEE ,  Jae Hyeok LEE ,  Hyun Yeul LEE ,  Hyeon Cheon JO ,  Doo Soon CHOI ,  Kyung Wha HONG ,  Da Som LEE ,  Yong Joon JEON

IPC: G06F3/0488 ,  G06F3/16 ,  G06F3/0482 ,  G06F3/01

Abstract: An electronic device is provided. The electronic device includes a housing, a touch screen display that includes a first edge and a second edge, a microphone, at least one speaker, a wireless communication circuit, a memory, and a processor operably connected with the touch screen display, the microphone, the at least one speaker, the wireless communication circuit, and the memory. The processor is configured to output a home screen including a plurality of application icons in a matrix pattern. The processor is configured receive an input from the first edge to the second edge. The processor is configured output a user interface on the touch screen display that includes a button that allows user to call a first operation and a plurality of cards. To call the first operation the processor is configured to receive a user input, transmit data and receive a response, and perform a task.

公开(公告)号：US20170345884A1

公开(公告)日：2017-11-30

申请号：US15444455

申请日：2017-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Hun CHOI ,  Young Tak KIM ,  Da Il EOM ,  Sun Jung LEE

IPC: H01L49/02 ,  H01L29/78 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/7851

Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.

公开(公告)号：US20170141107A1

公开(公告)日：2017-05-18

申请号：US15333545

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L29/423 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.