公开(公告)号：US20170263722A1

公开(公告)日：2017-09-14

申请号：US15408815

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gun YOU ,  Gi Gwan PARK ,  Sug Hyun SUNG ,  Myung Yoon UM ,  Dong Suk SHIN

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/775 ,  H01L29/7848

Abstract: A semiconductor device includes a first gate electrode on a substrate, a first trench on a first side of the first gate electrode, a second trench on a second side of the first gate electrode, a depth of the second trench being greater than a depth of the first trench, a first source/drain filling the first trench, and a second source/drain filling the second trench, a height of an upper surface of the second source/drain being greater than a height of the first source/drain.

公开(公告)号：US20170092728A1

公开(公告)日：2017-03-30

申请号：US15272456

申请日：2016-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Jung Gun YOU ,  Gi Gwan PARK ,  Dong Suk SHIN ,  Jin Wook KIM

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L27/088

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having first and second regions, a first fin-type pattern and a second fin-type pattern formed in the first region and extending in a first direction, and a third fin-type pattern and a fourth fin-type pattern formed in the second region and extending in a third direction. A first source/drain is formed on the first fin-type pattern and a second source/drain region is formed on the second fin-type pattern. Each of first and second source/drains have a cross section defining a same convex polygonal shape. A third source/drain is formed on the third fin-type pattern and a fourth source/drain region is formed on the fourth fin-type pattern. Cross-sections of the third and fourth source/drains define different convex polygonal shapes from one another.

公开(公告)号：US20240153948A1

公开(公告)日：2024-05-09

申请号：US18415863

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5283 ,  H01L29/42364 ,  H01L29/42372 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US20240038841A1

公开(公告)日：2024-02-01

申请号：US18188399

申请日：2023-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gi Gwan PARK ,  Jung Gun You ,  Sun Jung Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/41733

Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

公开(公告)号：US20170213826A1

公开(公告)日：2017-07-27

申请号：US15413680

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn KIM ,  Gi Gwan PARK

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7854

Abstract: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer

公开(公告)号：US20200043807A1

公开(公告)日：2020-02-06

申请号：US16599313

申请日：2019-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Gwan PARK ,  Jung Gun YOU ,  Ki Il KIM ,  Sug Hyun SUNG ,  Myung Yoon UM

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

公开(公告)号：US20180158836A1

公开(公告)日：2018-06-07

申请号：US15869599

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Soon KIM ,  Hyun Ji KIM ,  Jeong Yun LEE ,  Gi Gwan PARK ,  Sang Duk PARK ,  Young Mook OH ,  Yong Seok LEE

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/7853

Abstract: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

公开(公告)号：US20180114791A1

公开(公告)日：2018-04-26

申请号：US15850183

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gi Gwan PARK ,  Jung Gun YOU ,  Dong Suk SHIN ,  Hyun Yul CHOI

IPC: H01L27/092 ,  H01L21/84 ,  H01L27/02 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.

公开(公告)号：US20170222006A1

公开(公告)日：2017-08-03

申请号：US15298746

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Chan SUH ,  Yong Suk TAK ,  Gi Gwan PARK ,  Mi Seon PARK ,  Moon Seung YANG ,  Seung Hun LEE ,  Poren TANG

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L29/42376 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/66439 ,  H01L29/7831

Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern

公开(公告)号：US20250113597A1

公开(公告)日：2025-04-03

申请号：US18978581

申请日：2024-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo KIM ,  Gi Gwan PARK ,  Jung Hun CHOI ,  Koung Min RYU ,  Sun Jung LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L27/092 ,  H01L29/423 ,  H01L29/739

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.