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公开(公告)号：US20240232581A9
公开(公告)日：2024-07-11
申请号：US18450839
申请日：2023-08-16
发明人： Jung Ho AHN , Sun Jung LEE , Jae Wan CHOI
IPC分类号： G06N3/0455
CPC分类号： G06N3/0455
摘要： A device including processors configured to execute instructions and memories storing the instructions, which when executed by the processors configure the processors to perform an operation for training a transformer model having a plurality of encoders and a plurality of decoders by configuring the processors to identify the batches of training data into a plurality of micro-batches, select layer pairs for the plurality of micro-batches, assemble a processing order of the layer pairs, determining resource information to be allocated to the layer pairs, and allocate resources to the layer pairs based on the determined resource information to be allocated to the layer pairs, dependent con the processing order of the layer pairs.
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公开(公告)号：US20240184630A1
公开(公告)日：2024-06-06
申请号：US18526603
申请日：2023-12-01
发明人： Jung Ho AHN , Sun Jung LEE , Jae Wan CHOI , Seung Hwan HWANG
CPC分类号： G06F9/5027 , G06F5/01 , G06F15/8046
摘要： A device and method with batch normalization are provided. An accelerator includes: core modules, each core module including a respective plurality of cores configured to perform a first convolution operation using feature map data and a weight; local reduction operation modules adjacent to the respective core modules, each including a respective plurality of local reduction operators configured to perform a first local operation that obtains first local statistical values of the corresponding core module; a global reduction operation module configured to perform a first global operation that generates first global statistical values of the core module based on the first local statistical values of the core modules; and a normalization operation module configured to perform a first normalization operation on the feature map data based on the first global statistical values.
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3.发明申请MEMORY DEVICE, MEMORY MODULE INCLUDING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 有权存储器件，包括其的存储器模块和包括其的存储器系统公开(公告)号：US20160240242A1
公开(公告)日：2016-08-18
申请号：US14734101
申请日：2015-06-09
发明人： Young Hoon SON , Jung Ho AHN , Seong Il O
IPC分类号： G11C11/4094 , G11C11/4096 , G11C11/4091 , G06F3/06
CPC分类号： G11C11/4094 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C7/1063 , G11C11/4076 , G11C11/4091 , G11C11/4096
摘要： A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.
摘要翻译： 存储器件包括第一存储单元，第二存储单元，预充电电路，读出放大器，开关电路和控制器。 第一存储单元连接到第一位线，第二存储单元连接到第二位线，并且预充电电路连接在第一位线和第二位线之间。 读出放大器包括第一输入端和第二输入端。 开关电路连接到第一位线和第一输入端以及第二位线和第二输入端，并且被配置为控制第一位线和第一输入端之间的连接以及第二位之间的连接 线路和第二输入端子响应于开关信号。 控制器被配置为响应于命令产生开关信号。
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公开(公告)号：US20240135147A1
公开(公告)日：2024-04-25
申请号：US18450839
申请日：2023-08-15
发明人： Jung Ho AHN , Sun Jung LEE , Jae Wan CHOI
IPC分类号： G06N3/0455
CPC分类号： G06N3/0455
摘要： A device including processors configured to execute instructions and memories storing the instructions, which when executed by the processors configure the processors to perform an operation for training a transformer model having a plurality of encoders and a plurality of decoders by configuring the processors to identify the batches of training data into a plurality of micro-batches, select layer pairs for the plurality of micro-batches, assemble a processing order of the layer pairs, determining resource information to be allocated to the layer pairs, and allocate resources to the layer pairs based on the determined resource information to be allocated to the layer pairs, dependent con the processing order of the layer pairs.
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公开(公告)号：US20210043248A1
公开(公告)日：2021-02-11
申请号：US16858468
申请日：2020-04-24
发明人： Eojin LEE , Ingab KANG , Jung Ho AHN
IPC分类号： G11C11/406 , G11C11/4076 , G11C11/4072 , G11C11/408 , G11C11/409
摘要： A row hammer prevention circuit for providing a reference address to perform an additional refresh operation includes a history storage circuit configured to store one or more first addresses, each of the first addresses having been provided as the reference address. The row hammer prevention circuit further includes an address storage circuit configured to store a row address corresponding to an active command, a reference address storage circuit configured to store one or more second addresses, and a control circuit configured to provide the reference address in response to a refresh command.
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6.发明公开公开(公告)号：US20240079042A1
公开(公告)日：2024-03-07
申请号：US18268651
申请日：2021-01-11
发明人： Jung Ho AHN , Micheal Jae Min KIM , Nam Hoon KIM , Jae Hyun PARK
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： Proposed are counter-based selective row hammer refresh apparatus and method for row hammer prevention and, more particularly, proposed are an apparatus and a method for reducing energy consumption of dynamic random access memory (DRAM) by improving counter-based algorithms for solving a row hammer problem when applying a refresh management (RFM) command that is a new command applied to the latest DRAM standards, such as DDR5, LPDDR5, and the like.
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公开(公告)号：US20170091025A1
公开(公告)日：2017-03-30
申请号：US15059102
申请日：2016-03-02
发明人： Jung Ho AHN , Namsung KIM
CPC分类号： G06F11/1024 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1048 , H03M13/19 , H03M13/2909 , H03M13/2927
摘要： A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips. The method for the error correction of memory may include reading, by a first ECC engine unit included in each of a plurality of memory chips, a chunk including a plurality of data bursts, first parity bits, and position bits from each of the plurality of memory chips; extracting, by the first ECC engine unit, a single data burst having an error from the plurality of data bursts using the position bits; and performing, by the first ECC engine unit, first error correction using the first parity bit corresponding to the extracted error data burst.
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8.发明申请公开(公告)号：US20210263870A1
公开(公告)日：2021-08-26
申请号：US17143539
申请日：2021-01-07
发明人： Seung Wook LEE , Jung Ho AHN , Hweesoo KIM
摘要： An accelerator, an operation method of the accelerator, and an accelerator apparatus including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a main processor, performing at least one operation involved with the workloads in an internal memory of the accelerator or in a direct memory access (DMA) configured to control data input to or output from the internal memory, and providing a result of performing the at least one operation.
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公开(公告)号：US20230138659A1
公开(公告)日：2023-05-04
申请号：US17887145
申请日：2022-08-12
发明人： Jung Ho AHN , Sunjung LEE , Hailong LI , Jaewan CHOI
IPC分类号： G06N3/04
摘要： A device and method with transformer model implementation are provided. The electronic device includes a processor configured to perform an inference by implementing a transformer model including a plurality of encoders and a plurality of decoders, and a memory configured to store instructions to be executed by the processor. Each of the encoders and the decoders includes an attention block that determines an attention value. The processor is configured to perform a first sub-softmax tile-wise operation in the attention block, perform a reduction operation to determine an adjustment factor based on a resulting value of the first sub-softmax operation, and perform a second sub-softmax tile-wise operation based on a resulting value of the reduction operation.
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公开(公告)号：US20220365891A1
公开(公告)日：2022-11-17
申请号：US17876116
申请日：2022-07-28
发明人： Seung Wook LEE , Hweesoo KIM , Jung Ho AHN
摘要： An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.
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