公开(公告)号：US20240315023A1

公开(公告)日：2024-09-19

申请号：US18489451

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Woosung YANG ,  Jimo GU ,  Sukkang SUNG

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5223 ,  H10B41/27

Abstract: Disclosed are semiconductor devices which may include a substrate having first and second regions, a stack structure including electrode patterns and dielectric patterns, channels vertically penetrating the stack structure on the first region, a planarized dielectric layer covering the stack structure, and wiring patterns on the planarized dielectric layer. The dielectric pattern includes a first dielectric pattern on the first region, and a second dielectric pattern on the second region. The second dielectric pattern includes a first sub-dielectric pattern and a second sub-dielectric pattern. A dielectric constant of the first sub-dielectric patterns is greater than that of the first dielectric patterns and that of the second sub-dielectric patterns.

公开(公告)号：US20240038660A1

公开(公告)日：2024-02-01

申请号：US18197283

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Woosung YANG ,  Jimo GU ,  Jaeho KIM ,  Sukkang SUNG

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L25/0652

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region. A memory stack includes a plurality of word lines extending in the memory cell region and the connection region in a horizontal direction that is parallel with an upper surface of the substrate. The plurality of word lines overlaps with each other in a vertical direction. A support is in the connection region and positioned at a side of the memory stack. The support includes a plurality of steps. A plurality of pad parts is on a top surface of the support. A plurality of contact plugs passes through at least some of the plurality of word lines in the vertical direction. The plurality of contact plugs directly contacts the plurality of pad parts for electrical connection therewith.

公开(公告)号：US20230378083A1

公开(公告)日：2023-11-23

申请号：US18172534

申请日：2023-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H01L2223/54426

Abstract: A semiconductor device may include an align key on a plate layer. The align key may include a first align layer connected to a second align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The second align layer may be on the first align layer and may have a third length. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The third length may be smaller than the second length in the second direction.

公开(公告)号：US20230005947A1

公开(公告)日：2023-01-05

申请号：US17715508

申请日：2022-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemin YOO ,  Woosung YANG ,  Sukkang SUNG ,  Ahreum LEE

IPC: H01L27/11573 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11582

Abstract: A semiconductor device includes a first structure having first and second memory regions, an extension region therebetween, and word lines; and a second structure having a circuit region overlapping the extension region. The word lines include first and second common word lines at different levels, and first and second intermediate individual word lines at a same level and spaced apart. Each of the first and second common word lines are in the first and second memory regions and the extension region. The first intermediate individual word line is in the first memory region and extends into the extension region at a level between the first and second common word lines. The second intermediate individual word line is in the second memory region and extends into the extension region. The circuit region includes pass transistors connected to the word lines. A pass transistor overlaps the word lines in the extension region.