公开(公告)号：US09082750B2

公开(公告)日：2015-07-14

申请号：US14218293

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Albert Fayrushin ,  Kwang Soo Seol ,  Jaeduk Lee

IPC: H01L29/788 ,  H01L29/76 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

Abstract translation: 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

公开(公告)号：US20140197471A1

公开(公告)日：2014-07-17

申请号：US14218293

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Albert Fayrushin ,  Kwang Soo Seol ,  Jaeduk Lee

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

Abstract translation: 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

公开(公告)号：US20150236111A1

公开(公告)日：2015-08-20

申请号：US14683635

申请日：2015-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Hyun Lee ,  Byung-Kyu Cho ,  Jang-Hyun You ,  Albert Fayrushin

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/42364 ,  H01L21/02109 ,  H01L21/02304 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

Abstract translation: 非易失性存储器件包括栅极结构，绝缘层图案和隔离结构。 在第一方向上彼此间隔开的多个栅极结构形成在基板上。 栅结构的栅极在基本上垂直于第一方向的第二方向上延伸。 衬底包括在第二方向上交替且重复地形成的有源区和场区。 绝缘层图案形成在栅极结构之间并且其中具有第二气隙。 在每个场区域的基板上形成有在第一方向上延伸并且在栅极结构之间具有第一空气间隙，绝缘层图案和隔离结构的隔离结构。