公开(公告)号：US20220028449A1

公开(公告)日：2022-01-27

申请号：US17443480

申请日：2021-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur GUPTA ,  Manish Chandra JOSHI ,  Parvinder Kumar RANA

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/06 ,  G11C5/14

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

公开(公告)号：US20220103163A1

公开(公告)日：2022-03-31

申请号：US17175818

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur GUPTA ,  Lava Kumar PULLURU ,  Parvinder Kumar RANA

IPC: H03K3/356 ,  H03K19/0185 ,  G11C11/412 ,  G11C11/419

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the A output of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

公开(公告)号：US20160057093A1

公开(公告)日：2016-02-25

申请号：US14643133

申请日：2015-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： You-Bi SEO ,  Ananya VETAL ,  Ankur GUPTA ,  Ankur SARDANA ,  Yoon-Sun CHO ,  Hwa-Youn SUH

IPC: H04L12/58 ,  G06F3/0484

Abstract: A method is provided comprising: displaying a first screen including a plurality of messages received from at least a first contact and a second contact; detecting a selection of the first contact; in response to the selection, hiding from the first screen a first message in the plurality that is received from the first contact.

Abstract translation: 提供了一种方法，包括：显示包括从至少第一接触和第二接触接收的多个消息的第一屏幕; 检测所述第一接触的选择; 响应于选择，从第一屏幕隐藏从第一联系人接收的多个中的第一消息。

公开(公告)号：US20200075070A1

公开(公告)日：2020-03-05

申请号：US16166647

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ankur GUPTA ,  Abhishek KESARWANI ,  Parvinder Kumar RANA ,  Manish Chandra JOSHI ,  Lava Kumar PULLURU

IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

公开(公告)号：US20190147943A1

公开(公告)日：2019-05-16

申请号：US16190278

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Parvinder Kumar RANA ,  Lava Kumar PULLURU ,  Shuvadeep Kumar ,  Ankur GUPTA

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/222 ,  G11C8/08 ,  G11C8/18 ,  G11C11/418

Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.