公开(公告)号：US09373698B2

公开(公告)日：2016-06-21

申请号：US14505662

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Sun Kim ,  Jae-Kyung Seo ,  Ji-Ho Kim ,  Kwang-Sub Yoon ,  Bum-Joon Youn ,  Ki-Man Lee

IPC: H01L23/52 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/027 ,  H01L29/51

CPC classification number: H01L29/66636 ,  H01L21/0276 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7834

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成隔离层图案，以限定由隔离层图案覆盖的场区域和未被隔离层图案覆盖并从隔离层突出的第一和第二有源区域 模式。 第一抗反射层形成在隔离层图案上。 在基板的第一和第二有源区域和第一抗反射层上形成第一光致抗蚀剂层。 部分蚀刻第一光致抗蚀剂层以形成覆盖第一有源区的第一光致抗蚀剂图案。 将杂质注入到第二有源区中以形成第一杂质区。

公开(公告)号：US09105694B2

公开(公告)日：2015-08-11

申请号：US14286170

申请日：2014-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Ho Lee ,  Min-Keun Kwak ,  Bum-Joon Youn ,  Sung-Won Choi

IPC: H01L21/44 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823842 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66545

Abstract: A method for making a semiconductor device includes forming a trench in a first layer on a substrate. A conductive layer having a pattern is formed in the trench. A first metal gate electrode is formed on the conductive layer, and a second metal gate electrode is formed on the first metal gate electrode. The first and second metal gate electrodes at least partially conform to the pattern of the conductive layer. Widths of first surfaces of the first and second metal gate electrodes are different from respective widths of second surfaces of the first and second metal gate electrodes as a result of the pattern.

Abstract translation: 制造半导体器件的方法包括在衬底上的第一层中形成沟槽。 在沟槽中形成具有图案的导电层。 第一金属栅电极形成在导电层上，第二金属栅电极形成在第一金属栅电极上。 第一和第二金属栅电极至少部分地符合导电层的图案。 作为图案的结果，第一和第二金属栅电极的第一表面的宽度不同于第一和第二金属栅电极的第二表面的宽度。