公开(公告)号：US20240387495A1

公开(公告)日：2024-11-21

申请号：US18508143

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo LEE ,  Joonho JUN ,  Duk Sung KIM ,  Byoungkon JO

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/535 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package according to an example includes a base die having a first surface and a second surface opposite each other; a first group of core dies stacked on the first surface of the base die and electrically connected to the base die; a mount member facing the second surface of the base die; a second group of core dies between the base die and the mount member, the second group of core dies being stacked on the second surface of the base die and electrically connected to the base die; and an interface for an electrical connection between the base die and the mount member.

公开(公告)号：US20240427715A1

公开(公告)日：2024-12-26

申请号：US18588099

申请日：2024-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOONHO JUN ,  Minwoo LEE ,  Byoungkon JO ,  Duksung KIM ,  Doohee HWANG

IPC: G06F13/16 ,  G06F13/40 ,  G11C11/42

Abstract: An optical memory module includes a substrate, a first memory controller on the substrate, and a plurality of first memory devices on the substrate. The first memory controller includes the first transceiver. The first transceiver receives a first optical input signal through a first optical interconnection or outputs a first optical output signal through the first optical interconnection. The first memory controller is optically connected to an optical logic module located outside the optical memory module through the first transceiver and the first optical interconnection. The plurality of first memory devices are controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the first transceiver and the first optical interconnection.

公开(公告)号：US20240177750A1

公开(公告)日：2024-05-30

申请号：US18144531

申请日：2023-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungkon JO ,  Gyesik OH ,  Wangyong IM ,  Duk Sung KIM ,  Jangseok CHOI

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1096 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1093

Abstract: A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory devide, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing. In some embodiments, the semiconductor memory device is electrically and physically coupled to a central processing unit by hybrid copper bonding.