公开(公告)号：US20180286808A1

公开(公告)日：2018-10-04

申请号：US15820509

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho You ,  Sang Young Kim ,  Byung Chan Ryu

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.

公开(公告)号：US10374085B2

公开(公告)日：2019-08-06

申请号：US15997793

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Young Kim ,  Deok Han Bae ,  Byung Chan Ryu ,  Da Un Jeon

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

公开(公告)号：US10361159B2

公开(公告)日：2019-07-23

申请号：US15820509

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho You ,  Sang Young Kim ,  Byung Chan Ryu

IPC: H01L21/76 ,  H01L21/82 ,  H01L29/41 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L21/768 ,  H01L29/45 ,  H01L21/8234 ,  H01L23/532

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.

公开(公告)号：US11362211B2

公开(公告)日：2022-06-14

申请号：US17137850

申请日：2020-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Young Kim ,  Deok Han Bae ,  Byung Chan Ryu ,  Da Un Jeon

IPC: H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

公开(公告)号：US10529859B2

公开(公告)日：2020-01-07

申请号：US15988623

申请日：2018-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chan Ryu ,  Jong Ho You ,  Hyung Jong Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/165

Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

公开(公告)号：US11804528B2

公开(公告)日：2023-10-31

申请号：US17325466

申请日：2021-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Young Kim ,  Byung Chan Ryu ,  Da Un Jeon

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/45 ,  H01L29/423 ,  H01L23/528 ,  H01L23/532 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41733 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/456 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain pattern on the substrate, the source/drain pattern being at a side of the gate structure, a source/drain contact filling on and connected to the source/drain pattern, an entire top surface of the source/drain contact filling being lower than a top surface of the gate structure, and a connection contact directly on and connected to the source/drain contact filling, a top surface of the connection contact being higher than the top surface of the gate structure.

公开(公告)号：US10886404B2

公开(公告)日：2021-01-05

申请号：US16514067

申请日：2019-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Young Kim ,  Deok Han Bae ,  Byung Chan Ryu ,  Da Un Jeon

IPC: H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

公开(公告)号：US20190148538A1

公开(公告)日：2019-05-16

申请号：US15988623

申请日：2018-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chan Ryu ,  Jong Ho You ,  Hyung Jong Lee

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L23/522

Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.