公开(公告)号：US10361159B2

公开(公告)日：2019-07-23

申请号：US15820509

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho You ,  Sang Young Kim ,  Byung Chan Ryu

IPC: H01L21/76 ,  H01L21/82 ,  H01L29/41 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L21/768 ,  H01L29/45 ,  H01L21/8234 ,  H01L23/532

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.

公开(公告)号：US10529859B2

公开(公告)日：2020-01-07

申请号：US15988623

申请日：2018-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chan Ryu ,  Jong Ho You ,  Hyung Jong Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/165

Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

公开(公告)号：US20190148538A1

公开(公告)日：2019-05-16

申请号：US15988623

申请日：2018-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Chan Ryu ,  Jong Ho You ,  Hyung Jong Lee

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L23/522

Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

公开(公告)号：US10141447B2

公开(公告)日：2018-11-27

申请号：US15841515

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho You ,  Deok Han Bae ,  Sang Young Kim

IPC: H01L29/786 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/16 ,  H01L29/417 ,  H01L29/161

Abstract: A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate structure intersects the active fin and covers an upper portion of the active fin. A source/drain region is positioned on the active fin adjacent to the gate structure. A silicide layer is on the source/drain region. A contact plug is connected to the source/drain region. A void is present between the silicide layer and the contact plug.

公开(公告)号：US20180286810A1

公开(公告)日：2018-10-04

申请号：US15841515

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho You ,  Deok Han Bae ,  Sang Young Kim

IPC: H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/78618 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/45

Abstract: A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate structure intersects the active fin and covers an upper portion of the active fin. A source/drain region is positioned on the active fin adjacent to the gate structure. A silicide layer is on the source/drain region. A contact plug is connected to the source/drain region. Avoid is present between the silicide layer and the contact plug.

公开(公告)号：US20180286808A1

公开(公告)日：2018-10-04

申请号：US15820509

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho You ,  Sang Young Kim ,  Byung Chan Ryu

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.