公开(公告)号：US20240332059A1

公开(公告)日：2024-10-03

申请号：US18390026

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngin KIM ,  BYOUNGHO KWON ,  Yeil KIM ,  JONGHYUK PARK ,  JIN-WOO BAE ,  KYOUNGJOON SONG ,  MYUNGJAE JANG ,  Byungsoo JOO

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/762 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76831 ,  H01L21/76832

Abstract: A method of fabricating a semiconductor device includes forming, in a semiconductor substrate, a device isolation trench defining active regions, forming a first liner dielectric layer covering a top surface of the semiconductor substrate and an inner wall of the device isolation trench, forming a second liner dielectric layer covering the first liner dielectric layer, forming a buried dielectric layer filling the device isolation trench, performing a polishing process on the second liner dielectric layer and the buried dielectric layer to form a device isolation structure, forming a mask pattern running across the active regions, and partially patterning the active regions and the device isolation structure to form gate trenches. After the polishing process, the first liner dielectric layer, the second liner dielectric layer, and the buried dielectric layer have their top surfaces formed by the polishing process coplanar with each other.

公开(公告)号：US20240147697A1

公开(公告)日：2024-05-02

申请号：US18308376

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee LEE ,  Byoungho KWON ,  Seongeun KIM ,  Sujeong KIM ,  Jonghyuk PARK ,  Ilyoung YOON ,  Woohyuk JANG ,  Byungsoo JOO

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/482

Abstract: A semiconductor device includes a substrate, a chip region in the substrate, a scribe lane region in the substrate, first active patterns in the chip region, a first device isolation pattern on the first active patterns, second active patterns in the scribe lane region, and a second device isolation pattern on the second active patterns. The scribe lane region is adjacent to the chip region. The first device isolation pattern includes a first device isolation material, and the second device isolation pattern includes a second device isolation material. The second device isolation material is different from the first device isolation material.