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    SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTION STRUCTURE
    1.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTION STRUCTURE 审中-公开

    公开(公告)号：US20240014068A1

    公开(公告)日：2024-01-11

    申请号：US18217724

    申请日：2023-07-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yanghee LEE ,  Byoungho KWON ,  Jonghyuk PARK ,  Boun YOON ,  Ilyoung YOON ,  Seokjun HONG

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

    CPC classification number: H01L21/76832 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53238 ,  H01L21/76816 ,  H01L23/53295 ,  H10B12/315

    Abstract: A semiconductor device includes a lower structure; an intermediate insulating structure on the lower structure; an intermediate interconnection structure penetrating through the intermediate insulating structure; an upper insulating structure on the intermediate insulating structure and the intermediate interconnection structure; and an upper conductive pattern penetrating through the upper insulating structure and electrically connected to the intermediate interconnection structure, wherein the intermediate insulating structure includes an intermediate etch-stop layer and an intermediate insulating layer thereon, the intermediate insulating layer includes first and second intermediate material layers, the second intermediate material layer having an upper surface coplanar with an upper surface of the first intermediate material layer, the intermediate interconnection structure penetrates through the first intermediate material layer and the intermediate etch-stop layer, and a material of the first intermediate material layer has a dielectric constant that is higher than a dielectric constant of a material of the second intermediate material layer.

    WIRING STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    3.
    发明公开
    WIRING STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240194597A1

    公开(公告)日：2024-06-13

    申请号：US18527687

    申请日：2023-12-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghoon KWON ,  Yanghee LEE ,  Jonghyuk PARK

    IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

    CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L28/90 ,  H10B12/315

    Abstract: A wiring structure includes a substrate; a lower insulating layer on the substrate; a lower wiring structure extending in a vertical direction and passing through the lower insulating layer; a spacer surrounding a side wall of the lower wiring structure; a capping insulating layer on the lower insulating layer; and a via structure extending in the vertical direction and passing through the capping insulating layer, wherein the via structure overlaps the lower wiring structure and the spacer in the vertical direction, and the via structure includes a protruding portion extending in the vertical direction and passing through at least a portion of the spacer.

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200212047A1

    公开(公告)日：2020-07-02

    申请号：US16814387

    申请日：2020-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jonghyuk PARK ,  Byoungho KWON ,  Inho KIM ,  Hyesung PARK ,  Jin-Woo BAE ,  Yanghee LEE ,  Inseak HWANG

    IPC: H01L27/108

    Abstract: A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250133733A1

    公开(公告)日：2025-04-24

    申请号：US18886045

    申请日：2024-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyesung PARK ,  Jonghyuk PARK ,  Seungji KANG ,  Seongeun KIM ,  Jinwoo BAE ,  Dongwon LEE ,  Juyeon HAN

    IPC: H10B12/00

    Abstract: A semiconductor device may include a substrate with a memory cell area including a first active area and a peripheral circuit area including a second active area, a capacitor structure including a first electrode connected to the first active area in the memory cell area, a second electrode including a silicon containing layer surrounding the first electrode on the memory cell area and a metal plate layer on the silicon containing layer, an interlayer insulating layer on the peripheral circuit area, and a capping insulating layer covering the capacitor structure on the memory cell area and covering the interlayer insulating layer on the peripheral circuit area. The capacitor structure may include a capacitor dielectric layer between the first and second electrode. The metal plate layer may be on an upper surface of the silicon containing layer and may not be on a side surface of the silicon containing layer.

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING FORMING A RECESS FILLING PATTERN
    8.
    发明公开
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING FORMING A RECESS FILLING PATTERN 审中-公开

    公开(公告)号：US20230260828A1

    公开(公告)日：2023-08-17

    申请号：US18092239

    申请日：2022-12-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngin KIM ,  Jonghyuk PARK ,  Byoungho KWON

    IPC: H01L21/762 ,  H01L29/66

    CPC classification number: H01L21/76229 ,  H01L29/66621

    Abstract: A manufacturing method of a semiconductor device includes: etching a substrate, thereby forming a cell trench and a dummy trench; forming a preliminary isolation structure on the substrate, wherein a first dummy recess is formed in the preliminary isolation structure and overlaps with the dummy trench; forming a lower mask layer on the preliminary isolation structure, wherein a second dummy recess is formed in the lower mask layer and overlaps with the first dummy recess; forming a dummy recess filling pattern filling the second dummy recess; forming an upper mask layer on the lower mask layer and the dummy recess filling pattern; forming a gate trench using the lower mask layer and the upper mask layer as a mask; and forming a gate structure in the gate trench.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230005935A1

    公开(公告)日：2023-01-05

    申请号：US17713327

    申请日：2022-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yanghee LEE ,  Jonghyuk PARK ,  Ilyoung YOON ,  Boun YOON ,  Jeehwan HEO

    IPC: H01L27/108

    Abstract: A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20200227419A1

    公开(公告)日：2020-07-16

    申请号：US16833914

    申请日：2020-03-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jonghyuk PARK ,  Byoungho KWON ,  Inho KIM ,  Hyesung PARK ,  Jin-Woo BAE ,  Yanghee LEE ,  Inseak HWANG

    IPC: H01L27/108 ,  H01L21/66

    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

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