公开(公告)号：US20240079328A1

公开(公告)日：2024-03-07

申请号：US18133198

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun YOO ,  Changbeom KIM ,  Taejung SEOL

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a logic cell region on a substrate, an interconnection layer on the logic cell region, the interconnection layer including a plurality of metal layers on the logic cell region, and a first vertical structure in the interconnection layer, where the first vertical structure vertically connects the logic cell region to an uppermost metal layer of the plurality of metal layers, each of the plurality of unit structures includes a lower via, a lower interconnection line, an upper via, and an upper interconnection line, the lower interconnection line and the upper interconnection line of each respective unit structure of the plurality of unit structures cross each other, and the upper interconnection line of each of the plurality of unit structures includes a first upper interconnection line.

公开(公告)号：US20210409009A1

公开(公告)日：2021-12-30

申请号：US17340215

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon KANG ,  Changbeom KIM ,  Dalhee LEE ,  Wookyu KIM

IPC: H03K3/037 ,  G01R31/3177

Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

公开(公告)号：US20240128257A1

公开(公告)日：2024-04-18

申请号：US18481443

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dalhee LEE ,  Byounggon KANG ,  Wookyu KIM ,  Changbeom KIM ,  Minjung PARK ,  Taejun YOO

IPC: H01L27/02 ,  H03K19/20

CPC classification number: H01L27/0207 ,  H03K19/20

Abstract: An integrated circuit includes a plurality of cells in a series of rows, wherein a first cell of the plurality of cells includes a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to independently generate an output bit signal according to input bit signals, a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, a second input pin group including at least one input pin commonly connected to two or more logic circuits among the plurality of logic circuits, and a third input pin group including at least one input pin respectively connected exclusively to at least one of the plurality of logic circuits.