公开(公告)号：US20240128257A1

公开(公告)日：2024-04-18

申请号：US18481443

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dalhee LEE ,  Byounggon KANG ,  Wookyu KIM ,  Changbeom KIM ,  Minjung PARK ,  Taejun YOO

IPC: H01L27/02 ,  H03K19/20

CPC classification number: H01L27/0207 ,  H03K19/20

Abstract: An integrated circuit includes a plurality of cells in a series of rows, wherein a first cell of the plurality of cells includes a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to independently generate an output bit signal according to input bit signals, a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, a second input pin group including at least one input pin commonly connected to two or more logic circuits among the plurality of logic circuits, and a third input pin group including at least one input pin respectively connected exclusively to at least one of the plurality of logic circuits.

公开(公告)号：US20240079328A1

公开(公告)日：2024-03-07

申请号：US18133198

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun YOO ,  Changbeom KIM ,  Taejung SEOL

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a logic cell region on a substrate, an interconnection layer on the logic cell region, the interconnection layer including a plurality of metal layers on the logic cell region, and a first vertical structure in the interconnection layer, where the first vertical structure vertically connects the logic cell region to an uppermost metal layer of the plurality of metal layers, each of the plurality of unit structures includes a lower via, a lower interconnection line, an upper via, and an upper interconnection line, the lower interconnection line and the upper interconnection line of each respective unit structure of the plurality of unit structures cross each other, and the upper interconnection line of each of the plurality of unit structures includes a first upper interconnection line.

公开(公告)号：US20230029260A1

公开(公告)日：2023-01-26

申请号：US17722683

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeha LEE ,  Hyeongkyu KIM ,  Taejun YOO ,  Unseon CHEON

IPC: H01L27/02 ,  G06F30/392

Abstract: A semiconductor device according to an embodiment of the present inventive concept includes a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having one or more gate structures and one or more active regions, and in some standard cells providing the same circuit and in standard cell regions at different locations, input lines or/and output lines are at different locations.