公开(公告)号：US20240429168A1

公开(公告)日：2024-12-26

申请号：US18597387

申请日：2024-03-06

Applicant: Samsung Electronics Co., LTD.

Inventor： Dalhee LEE ,  Sangjung JEON

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit includes a plurality of standard cells on a front surface of a substrate and a backside wiring layer on a back surface of the substrate, where the plurality of standard cells include a first standard cell, the first standard cell includes a first P-type transistor and a first N-type transistor, the backside wiring layer includes a first backside wiring pattern configured to receive a first power supply voltage, a second backside wiring pattern configured to receive a second power supply voltage, and a third backside wiring pattern configured to receive a ground voltage, and the first standard cell at least partially overlaps the first backside wiring pattern, the second backside wiring pattern, and the third backside wiring pattern.

公开(公告)号：US20210135659A1

公开(公告)日：2021-05-06

申请号：US16886187

申请日：2020-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dalhee LEE ,  Byounggon KANG

IPC: H03K3/037 ,  H03K19/20 ,  G06F1/04

Abstract: An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set reset (SR) latch by being cross-coupled, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and an activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or a pull-down of a first node at which the first signal is generated.

公开(公告)号：US20210409009A1

公开(公告)日：2021-12-30

申请号：US17340215

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon KANG ,  Changbeom KIM ,  Dalhee LEE ,  Wookyu KIM

IPC: H03K3/037 ,  G01R31/3177

Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

公开(公告)号：US20240128257A1

公开(公告)日：2024-04-18

申请号：US18481443

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dalhee LEE ,  Byounggon KANG ,  Wookyu KIM ,  Changbeom KIM ,  Minjung PARK ,  Taejun YOO

IPC: H01L27/02 ,  H03K19/20

CPC classification number: H01L27/0207 ,  H03K19/20

Abstract: An integrated circuit includes a plurality of cells in a series of rows, wherein a first cell of the plurality of cells includes a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to independently generate an output bit signal according to input bit signals, a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, a second input pin group including at least one input pin commonly connected to two or more logic circuits among the plurality of logic circuits, and a third input pin group including at least one input pin respectively connected exclusively to at least one of the plurality of logic circuits.

公开(公告)号：US20220407504A1

公开(公告)日：2022-12-22

申请号：US17843585

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounggon KANG ,  Dalhee LEE

IPC: H03K3/037 ,  H03K19/20

Abstract: A flip-flop circuit includes a first master latch circuit transmitting an inverted signal of an input signal received from an external device to a first node and transmitting an inverted signal of a signal of the first node to a second node, according to a first control signal having a first logic level or a second control signal having a second logic level, a first slave latch circuit transmitting an inverted signal of a signal of the second node to a third node according to the first control signal having the second logic level or the second control signal having the first logic level, a first output inverter generating a first output signal by inverting a signal of the third node, and a first control signal generation circuit generating the first control signal and the second control signal based on a clock signal and the signal of the first node.