公开(公告)号：US20230077532A1

公开(公告)日：2023-03-16

申请号：US17946761

申请日：2022-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wookyu KIM ,  Changbeom Kim ,  Taejun Yoo ,  Seungmin Lee

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/327

Abstract: A standard cell and an integrated circuit including the same are is provided. The standard cell is provided in first and second rows. The standard cell includes: a first circuit region provided in the first row and including a plurality of first transistors; a second circuit region provided in the second row and including a plurality of second transistors; a first input pin provided in the first circuit region and configured to receive a first input signal; and a second input pin provided in the second circuit region and configured to receive a second input signal. The first input signal is input to gate terminals of each of the plurality of first transistors, and the second input signal is input to gate terminals of each of the plurality of second transistors. The first circuit region is symmetric with respect to a second horizontal direction and the second circuit region is symmetric with respect to the second horizontal direction.

公开(公告)号：US20210409009A1

公开(公告)日：2021-12-30

申请号：US17340215

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon KANG ,  Changbeom KIM ,  Dalhee LEE ,  Wookyu KIM

IPC: H03K3/037 ,  G01R31/3177

Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

公开(公告)号：US20240128257A1

公开(公告)日：2024-04-18

申请号：US18481443

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dalhee LEE ,  Byounggon KANG ,  Wookyu KIM ,  Changbeom KIM ,  Minjung PARK ,  Taejun YOO

IPC: H01L27/02 ,  H03K19/20

CPC classification number: H01L27/0207 ,  H03K19/20

Abstract: An integrated circuit includes a plurality of cells in a series of rows, wherein a first cell of the plurality of cells includes a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to independently generate an output bit signal according to input bit signals, a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, a second input pin group including at least one input pin commonly connected to two or more logic circuits among the plurality of logic circuits, and a third input pin group including at least one input pin respectively connected exclusively to at least one of the plurality of logic circuits.