公开(公告)号：US20250110649A1

公开(公告)日：2025-04-03

申请号：US18977123

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G06F3/06

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval, a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value, and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

公开(公告)号：US20240248610A1

公开(公告)日：2024-07-25

申请号：US18354919

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

IPC: G06F3/06 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0673 ,  G11C11/4074 ,  G11C11/4096

Abstract: A method for extending life expectancy of a volatile memory device includes performing a life test corresponding to memory cells included in the volatile memory device, determining whether the memory cells have a normal life state or a shrink-life state indicating a life expectancy that is reduced relative to the normal life state based on a result of the life test, and decreasing a wordline voltage, which is applied to a wordline connected to the memory cells, to a first voltage that is less than a second voltage that is applied to the wordline in the normal life state during a read operation or a write operation responsive to determining that the memory cells have the shrink-life state.

公开(公告)号：US12230312B2

公开(公告)日：2025-02-18

申请号：US18191039

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/4078

Abstract: A defense method of a memory device according to an embodiment includes obtaining a plurality of defense types to refresh a row of a memory cell array that is subjected to an attack, determining respective operation times for the defense types, and performing a refresh operation for the row of the memory cell array by switching among the defense types based on the respective operation times that were determined.

公开(公告)号：US20230410934A1

公开(公告)日：2023-12-21

申请号：US18163975

申请日：2023-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: A semiconductor device may include: a memory device that includes a memory cell, a page buffer, and a first switch having a first end that is electrically connected to a first node located at a bonding point of the memory cell and a second end that is connected to a second node located at the page buffer; and a memory controller that is configured to apply a pre-charge voltage to the first node and the second node in a first period, to close the first switch in a second period following the first period, and is configured to determine whether bonding between the memory cell and the first switch is defective based on a voltage of the second node after the first switch is closed.

公开(公告)号：US20230408554A1

公开(公告)日：2023-12-21

申请号：US18166656

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Bak ,  Junyoung Ko ,  Changhwi Park

IPC: G01R19/00 ,  G11C29/50

CPC classification number: G01R19/0038 ,  G11C29/50004 ,  G11C2029/5004

Abstract: A test device includes a power supply circuit that is configured to supply an input voltage through a power voltage pin to a memory device under test, and a test controller, which is configured to: (i) transmit a command signal to the memory device, (ii) measure a first current flowing to the memory device through the power voltage pin at a first time point after transmitting the command signal, (iii) measure a second current flowing to the memory device through the power voltage pin at a second time point, which is different from the first time point, and (iv) compare the measured first current to the measured second current to thereby determine whether the memory device has a defect therein.

公开(公告)号：US20250166689A1

公开(公告)日：2025-05-22

申请号：US19029019

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G11C11/406 ,  G11C11/4078

Abstract: A defense method of a memory device according to an embodiment includes obtaining a plurality of defense types to refresh a row of a memory cell array that is subjected to an attack, determining respective operation times for the defense types, and performing a refresh operation for the row of the memory cell array by switching among the defense types based on the respective operation times that were determined.

公开(公告)号：US12204772B2

公开(公告)日：2025-01-21

申请号：US18195587

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G06F3/06

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

公开(公告)号：US20240389364A1

公开(公告)日：2024-11-21

申请号：US18626299

申请日：2024-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkil Lee ,  Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

IPC: H10B80/00 ,  G06F12/0811 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18

Abstract: A computing device includes a first die that includes a logic structure that includes a processing device that performs computation with respect to data, a front side line structure disposed on a front surface of the logic structure and that includes lines, and a back side power network structure disposed on a back surface of the logic structure and that provides power. The computing device further includes a second die that includes a memory device that stores the data for the computation of the processing device. The memory device includes a plurality of bank groups that respectively correspond to a plurality of channels, and the second die is bonded onto the back side power network structure by a C2C bonding method.

公开(公告)号：US20240170039A1

公开(公告)日：2024-05-23

申请号：US18463659

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4096

Abstract: A CXL device includes at least one memory; a CXL controller configured to receive a request to access the at least one memory via a CXL interface, and to output a memory identifier indicating a first memory of the at least one memory, a command and a row address of the first memory based on the request; and a refresh controller configured to store the row address as a target row address of the first memory and further configured to generate a targeted refresh signal based on a number of receptions of the command for refreshing the target row address in the first memory.

公开(公告)号：US20240160362A1

公开(公告)日：2024-05-16

申请号：US18195587

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.