公开(公告)号：US20240170039A1

公开(公告)日：2024-05-23

申请号：US18463659

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4096

Abstract: A CXL device includes at least one memory; a CXL controller configured to receive a request to access the at least one memory via a CXL interface, and to output a memory identifier indicating a first memory of the at least one memory, a command and a row address of the first memory based on the request; and a refresh controller configured to store the row address as a target row address of the first memory and further configured to generate a targeted refresh signal based on a number of receptions of the command for refreshing the target row address in the first memory.

公开(公告)号：US20240160362A1

公开(公告)日：2024-05-16

申请号：US18195587

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

公开(公告)号：US20240079049A1

公开(公告)日：2024-03-07

申请号：US18338502

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Bak ,  Junyoung Ko ,  Changhwi Park

IPC: G11C11/4093 ,  G11C11/4074

CPC classification number: G11C11/4093 ,  G11C11/4074

Abstract: An electronic device includes a system on-chip that outputs a write clock and a write data signal, and a memory device that receives the write data signal based on the write clock and outputs a read data signal and a data strobe signal whose frequency is different from a frequency of the write clock. The memory device further includes a first interval oscillator, a second interval oscillator, and a temperature sensor. The electronic device performs a first training in initialization of the electronic device and performs a second training in an operation after the initialization. The memory device performs a counting operation during an operation of an interval oscillator in the second training and corrects a final count value with reference to temperature information of the memory device.

公开(公告)号：US20250110649A1

公开(公告)日：2025-04-03

申请号：US18977123

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G06F3/06

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval, a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value, and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

公开(公告)号：US20240248610A1

公开(公告)日：2024-07-25

申请号：US18354919

申请日：2023-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

IPC: G06F3/06 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0673 ,  G11C11/4074 ,  G11C11/4096

Abstract: A method for extending life expectancy of a volatile memory device includes performing a life test corresponding to memory cells included in the volatile memory device, determining whether the memory cells have a normal life state or a shrink-life state indicating a life expectancy that is reduced relative to the normal life state based on a result of the life test, and decreasing a wordline voltage, which is applied to a wordline connected to the memory cells, to a first voltage that is less than a second voltage that is applied to the wordline in the normal life state during a read operation or a write operation responsive to determining that the memory cells have the shrink-life state.

公开(公告)号：US11475956B2

公开(公告)日：2022-10-18

申请号：US17234175

申请日：2021-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaehoon Kim ,  Junyoung Ko ,  Sangwan Nam ,  Minjae Seo ,  Jiwon Seo ,  Hojun Lee

IPC: G11C16/08 ,  G11C16/20 ,  G11C16/16 ,  G11C16/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/26

Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

公开(公告)号：US08866295B2

公开(公告)日：2014-10-21

申请号：US14278751

申请日：2014-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ja Kim ,  Junyoung Ko ,  Daesang Chan

IPC: H01L23/498 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L23/3157 ,  H01L23/49811 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/838 ,  H01L2224/94 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/11

Abstract: The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon.

公开(公告)号：US20250166689A1

公开(公告)日：2025-05-22

申请号：US19029019

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G11C11/406 ,  G11C11/4078

Abstract: A defense method of a memory device according to an embodiment includes obtaining a plurality of defense types to refresh a row of a memory cell array that is subjected to an attack, determining respective operation times for the defense types, and performing a refresh operation for the row of the memory cell array by switching among the defense types based on the respective operation times that were determined.

公开(公告)号：US12204772B2

公开(公告)日：2025-01-21

申请号：US18195587

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

IPC: G06F3/06

Abstract: A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

公开(公告)号：US20240389364A1

公开(公告)日：2024-11-21

申请号：US18626299

申请日：2024-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkil Lee ,  Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

IPC: H10B80/00 ,  G06F12/0811 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18

Abstract: A computing device includes a first die that includes a logic structure that includes a processing device that performs computation with respect to data, a front side line structure disposed on a front surface of the logic structure and that includes lines, and a back side power network structure disposed on a back surface of the logic structure and that provides power. The computing device further includes a second die that includes a memory device that stores the data for the computation of the processing device. The memory device includes a plurality of bank groups that respectively correspond to a plurality of channels, and the second die is bonded onto the back side power network structure by a C2C bonding method.