公开(公告)号：US20220115496A1

公开(公告)日：2022-04-14

申请号：US17315947

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin PARK ,  Hanjin LIM ,  Haeryong KIM ,  Younglim PARK ,  Cheoljin CHO

IPC: H01L49/02

Abstract: An integrated circuit device including a first electrode layer including a first metal and having a first thermal expansion coefficient; a dielectric layer on the first electrode layer, the dielectric layer including a second metal oxide including a second metal that is different from the first metal, and having a second thermal expansion coefficient that is less than the first thermal expansion coefficient; and a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer.

公开(公告)号：US20240315003A1

公开(公告)日：2024-09-19

申请号：US18675175

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheoljin CHO ,  Jaesoon LIM ,  Jaehyoung CHOI ,  Jungmin PARK

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H01L28/55 ,  H01L28/65

Abstract: A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.

公开(公告)号：US20230328958A1

公开(公告)日：2023-10-12

申请号：US18205715

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheoljin CHO ,  Jaesoon LIM ,  Jaehyoung CHOI ,  Jungmin PARK

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H01L28/65 ,  H01L28/55

Abstract: A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.

公开(公告)号：US20240234315A9

公开(公告)日：2024-07-11

申请号：US18403259

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheoljin CHO ,  Jungmin PARK ,  Hanjin LIM ,  Jaehyoung CHOI

IPC: H01L23/528

CPC classification number: H01L23/5283 ,  H01L28/60 ,  H01L28/75 ,  H01L28/90

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode including an outer protective layer, a conductive layer between opposing sidewalls of the outer protective layer, and an inner protective layer between opposing sidewalls of the conductive layer, a first supporter pattern on a side surface of the lower electrode, the first supporter pattern including a supporter hole, a dielectric layer on a surface of each of the lower electrode and the first supporter pattern, and an upper electrode on the dielectric layer. The outer protective layer includes titanium oxide, the conductive layer includes titanium nitride, and the inner protective layer includes titanium silicon nitride. In a horizontal cross-sectional view, the outer protective layer has an arc shape that extends between the dielectric layer and the conductive layer.

公开(公告)号：US20240136286A1

公开(公告)日：2024-04-25

申请号：US18403259

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheoljin CHO ,  Jungmin PARK ,  Hanjin LIM ,  Jaehyoung CHOI

IPC: H01L23/528

CPC classification number: H01L23/5283 ,  H01L28/60 ,  H01L28/75 ,  H01L28/90

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode including an outer protective layer, a conductive layer between opposing sidewalls of the outer protective layer, and an inner protective layer between opposing sidewalls of the conductive layer, a first supporter pattern on a side surface of the lower electrode, the first supporter pattern including a supporter hole, a dielectric layer on a surface of each of the lower electrode and the first supporter pattern, and an upper electrode on the dielectric layer. The outer protective layer includes titanium oxide, the conductive layer includes titanium nitride, and the inner protective layer includes titanium silicon nitride. In a horizontal cross-sectional view, the outer protective layer has an arc shape that extends between the dielectric layer and the conductive layer.

公开(公告)号：US20220216296A1

公开(公告)日：2022-07-07

申请号：US17376458

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gabjin NAM ,  Youngbin LEE ,  Cheoljin CHO ,  Jaehyoung CHOI

IPC: H01L49/02 ,  H01L27/11507

Abstract: Provided is a method of fabricating a capacitor. The method of fabricating a capacitor may include forming a first electrode, forming a dielectric layer on the first electrode, forming a second electrode on the dielectric layer, and applying, between the first electrode and the second electrode, a voltage outside an operating voltage range applied during operation or a current outside an operating current range applied during operation.

公开(公告)号：US20220093603A1

公开(公告)日：2022-03-24

申请号：US17222006

申请日：2021-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheoljin CHO ,  Jaesoon LIM ,  Jaehyoung CHOI ,  Jungmin PARK

IPC: H01L27/108 ,  H01L49/02

Abstract: A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.