公开(公告)号：US11637019B2

公开(公告)日：2023-04-25

申请号：US17393201

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Sun Hwang ,  Han Sol Seok ,  Hyun Ku Kang ,  Byoung Ho Kwon ,  Chung Ki Min

IPC: H01L21/3105 ,  H01L25/065 ,  H01L21/762 ,  H01L27/11582 ,  H01L29/06 ,  H01L27/11556 ,  H01L21/78

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

公开(公告)号：US10535679B2

公开(公告)日：2020-01-14

申请号：US16136474

申请日：2018-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Boh Chang Kim ,  Chung Ki Min ,  Ji Hoon Park ,  Byung Kwan You

IPC: H01L27/11582 ,  H01L29/423 ,  H01L23/00

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

公开(公告)号：US11145672B2

公开(公告)日：2021-10-12

申请号：US16706684

申请日：2019-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Boh Chang Kim ,  Chung Ki Min ,  Ji Hoon Park ,  Byung Kwan You

IPC: H01L27/11582 ,  H01L23/00 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/538 ,  H01L27/11531

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

公开(公告)号：US11087990B2

公开(公告)日：2021-08-10

申请号：US16433218

申请日：2019-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Sun Hwang ,  Han Sol Seok ,  Hyun Ku Kang ,  Byoung Ho Kwon ,  Chung Ki Min

IPC: H01L27/11582 ,  H01L21/3105 ,  H01L25/065 ,  H01L21/762 ,  H01L29/06 ,  H01L27/11556 ,  H01L21/78

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.