公开(公告)号：US10673420B2

公开(公告)日：2020-06-02

申请号：US15981415

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Lee ,  Dae Seong Lee ,  Minsu Kim ,  Ahreum Kim ,  Chunghee Kim

IPC: H03K3/037 ,  H03K19/20 ,  G06F1/10 ,  G01R31/317 ,  G01R31/3177

Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

公开(公告)号：US11988712B2

公开(公告)日：2024-05-21

申请号：US17551974

申请日：2021-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chunghee Kim ,  Ahreum Kim ,  Minsu Kim ,  Seungman Lim

IPC: G01R31/3185

CPC classification number: G01R31/318541

Abstract: A multi-bit flip-flop includes a first flip-flop having a first output driver connected to a first output pin and arranged on a first row, a second flip-flop including a second output driver electrically connected to a second output pin and arranged on a second row, and an internal hold buffer connected to the first output driver on the first row and the second flip-flop on the second row.

公开(公告)号：US09779198B2

公开(公告)日：2017-10-03

申请号：US14832307

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daekwon Kang ,  Donggyun Kim ,  Jaeseok Yang ,  Jiyoung Jung ,  Chunghee Kim ,  Ha-Young Kim ,  Sungkeun Park ,  Younggook Park ,  Myungsoo Jang ,  Jintae Kim

IPC: G06F17/50 ,  G03F1/70

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081

Abstract: A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.