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1.发明申请NONVOLATILE MEMORY DEVICE COMPRISING PAGE BUFFER AND OPERATION METHOD THEREOF 审中-公开包含页面缓冲器的非易失性存储器件及其操作方法公开(公告)号：US20160012907A1
公开(公告)日：2016-01-14
申请号：US14853488
申请日：2015-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongku KANG , Dae Yeal LEE
CPC classification number: G11C16/3459 , G11C7/1039 , G11C11/56 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3481 , G11C17/06
Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.
Abstract translation: 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。
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2.发明申请NONVOLATILE MEMORY DEVICE COMPRISING PAGE BUFFER AND OPERATION METHOD THEREOF 有权包含页面缓冲器的非易失性存储器件及其操作方法公开(公告)号：US20140153329A1
公开(公告)日：2014-06-05
申请号：US14077606
申请日：2013-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongku KANG , Dae Yeal LEE
CPC classification number: G11C16/3459 , G11C7/1039 , G11C11/56 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3481 , G11C17/06
Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.
Abstract translation: 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。
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